This topic will be used to announce new features and other significant development updates during the KiCad 10 development cycle. KiCad 10 is expected to be released around February, 2026.
This topic is only for announcements. Please start new topics to discuss new features.
You can now import Altium projects and it will automatically link the schematic and pcb import items as well as any libraries that it finds
Daniel Treffenstädt has contributed support for IPC-4761 via protection features (filling, capping, etc in addition to tenting), which can be specified on a per-via basis and are included in drill file, IPC-2581, and ODB++ outputs.
You can now create “Local” power symbols. Whereas normal power symbols (hereafter “global power” symbols) will create a global label with the symbol value, local power symbols will create a local label.
Local power symbols also show a distinct “place marker” next to their value, allowing you to see that the power symbol has scope of only the current sheet.
Component Classes can now be dynamically assigned in the PCB editor. Matching conditions can be created from any combination of:
A few pointers as there isn’t yet documentation:
* and ? wildcards, for matching any number of characters, or matching one character respectively.You can now make textboxes “knockout” (for better control over the margins to the enclosing copper).
Create Array can now arrange existing items by selection order.
Box selection has also been tweaked to sort items by row, then column, instead of randomly. Cross-selection should preserve the selection order.
This allows quickly arranging items that tend to be laid out geographically:
Support for jumper symbols and footprints has been added. There are two ways to define jumper symbols/footprints: you can enable an option that will mark pins/pads with the same number as being internally connected, or you can explicitly define groups of pins/pads that should be considered internally connected. Jumpered pins/pads will always have the same net.
The status bar now reports the copper area of the selected items. Might be useful for determining heat-sinking, etc.
More of an under-the-hood rather than visible change, but a common issue with those working on length tuning has been that the calculations between the router (particularly the length tuning tools), the status bar, the PCB Net Inspector, and the DRC checks could return different values.
These have now been unified in to one common set of calculations, which apply uniform optimisations (e.g. removing lengths of stub vias, only considering via height between connected layers, and optimising electrical length when there are tracks in pads). There is room for further electrical length optimisation (such as colinear track removal, stub track removal, tracks-through-pads), but we now have the machinery in place to implement these in a common place. Note that in pathological routing cases there may still be differences in the lengths reported.
In addition, the PCB Net Inspector is now multi-threaded. In the past, it could be a performance overhead for complex boards. This is now significantly improved.
It is likely that some sensitive DRC rules may now report errors due to changes in optimisations and calculations being unified. User feedback most welcome to ensure this is working well.
Following on from the previous announcement of the unification of length calculation code, KiCad now supports time domain / propagation delay calculations, tuning, and DRC rules. At the moment, it is only possible to specify propagation delays by hand, but future work will aim to add empirical (formula-based) and 2D field solver propagation delays derived from trace geometries and stackup definition.
The workflow is:
Note that unit propagation speeds can be set up per-layer, and for vias. Unit propagation speeds can be input in units of ps/in, ps/cm, and ps/mm. Times may be input in units of ps and fs. It is also possible, for advanced simulated scenarios, to set up via overrides, which are specified based on the via start / end (e.g. to support blind and micro vias) and signal start / end layers.
As for other netclass fields, if there are multiple netclasses assigned to a net, the effective Delay Profile will be taken from the highest-profile netclass with a Delay Profile assigned.
Footprint pads now have a ‘Pad-to-die delay’ field, visible in the pad properties dialog and the properties panel.
Now, any measurements for nets matching assigned netclasses will display timing information in the status bar, and can show time information in the Net Inspector by choosing ‘Show Time Domain Details’ in the inspector configuration menu:
ps and fs:Testing welcome!
To assist with entering propagation delay values for the delay tuning setup above, the PCB Calculator now calculates unit propagation delays for microstrip, coplaner wave guide, coupled microstrip, and stripline geometries :
Groups are now available in the schematic editor.
