small tool added (by S.Hillbrand) to the context menu: Shape modification–> simplify polygon
Control over via tenting on top and bottom sides, at a board level and per-via overrides.
Note: this replaces the “tent vias” checkbox in the Plot dialog, which is now gone.
@JeffYoung added a feature that lets you create ERC/DRC errors and warnings from textboxes and fields:
New text variables:
${ERC_WARNING <custom title>}
${ERC_ERROR <custom title>}
${DRC_WARNING <custom title>}
${DRC_ERROR <custom title>}
Variables must be at the start of a field, text item or textbox to be recognised by ERC/DRC.
They resolve to the empty string on the canvas.
You can now embed various elements in your schematics, pcb layouts, footprints and symbols:
-
Worksheets
-
Datasheets:
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3d Models:
-
Fonts:
New ERC check for local and global labels with the same name (from Wishlist: ERC local/global net name collisions (#9461) · Issues · KiCad / KiCad Source Code / kicad · GitLab)
Nets can now have multiple netclasses assigned. This can be used for fine-grained, modular, custom DRC rules. New functionality includes:
- Introduces ordering of netclasses
- Allows netclasses to have null properties (except on the default netclass)
- Effective netclasses are constructed from non-null netclass fields in netclass priority order (with default netclass parameters always used as fallback)
- DRC checks for netclass equivalence as requiring both items to have the same set of constituent netclasses
- Modify DRC to test netclass name (A.netclass == ‘my_netclass’) against the comma-separated list of priority-ordered constituent netclasses
- Adds DRC function A.hasNetclass(‘my_netclass’) to test if a given netclass is assigned to an item
- Schematic and PCB netclass coloring taken from the effective aggregate netclass for a net
Note that we have also tidied up the case where previously the default netclass could have a schematic color assigned, but not a pcb color. Now, the default netclass can have neither color assigned. These should be set in the global color settings if customisation is required.
STEP export now supports exporting a subset of components based on what is selected in the PCB editor or a list of reference designators (supporting wildcards):
The latter is now supported in kicad-cli
with the --component-filter
option.
DRC skew rules now have an optional flag (within_diff_pairs)
. When set, the DRC rule is run independently for every identified differential pair in the traces which match the rule conditions. When left out, the current DRC behaviour remains whereby skew is run acros all matching nets (for example, for checking the skew of a bus). For example, for the following schematic:
With this board layout:
DRC with this rule:
(rule diff_skew
(constraint skew (max 3mil) (within_diff_pairs))
(condition "A.hasNetclass('DIFF_PAIR')"))
yields:
In addition, the router and DRC definition of skew have been unified to always be measured relative to the longest trace in the skew set (be that the longest in each diff pair, or the longest in all traces, depending on if (within_diff_pairs)
is set).
The router will also pick up the correct constraint for skew tuning where skew is definied using a (within_diff_pairs)
rule.
Layer pairs can be added to a preset list. “Enabled” pairs, along with the currently-set pair if not itself a preset, can be cycled with the “Shift+V” hotkey:
![Pcbnew_layer_pair_cycle_dialog](http://kicad-info.s3.dualstack.us-west-2.amazonaws.com/original/3X/b/8/b858e8eef4c2f92d2015e5e65e32a9f984ca5043.png)
There is a new Shape Modification tool next to Fillet and Chamfer: “Dogbone” corner relief for cutouts that have to fit something with square corners (specifically: sharper than the edge-routing milling bit, often 1 or 2mm):
The Position Relative tool can now use an arbitrary point as the reference (which can be snapped to objects)
In eeschema, net colors defined by netclasses can now be displayed in a highlighting style, by selecting the ‘Highlight net colors’ in the netclass setup panel (from discussion in Is it possible to make netlist colors look more like Altium? - #4 by JamesJ)