I’m facing a problem never encounter before with previous releases of KiCad. For this reason I attach one of the projects where I’m having troubles. I try to summarize in the shortest possible way:
The project is finished
The DRC doesn’t reveal any error nor warning
As soon as I create the gerber files, the pcb appears to be modified (never happened before in this phase)
I save the project
I redo the gerber files, this time the pcb is not modified
Running a DRC again reveals 17 DRC violations of type [lib_footprint_mismatch]
I update all the footprints that caused the 17 DRC violations
Running the DRC and this time I get zero violations
These violations are referred only to JST_XH_B3B-XH-A… connectors and PhoenixContact_MSTBA_2,5_4-G-5,08… connectors. I attach also a DRC report.
If I repeat the whole process again, also the violations are back again. All these violations are referred to standard stock footprints. I want to point out that I’m using symbols and footprints taken from GitHub and constantly updated. I suppose that those are identical to the footprints and symbols found in the official installer.
[lib_footprint_mismatch]: Footprint 'JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical' does not match copy in library 'Connector_JST'.
Local override; warning
@(281,0000 mm, 192,0000 mm): Footprint J9
[lib_footprint_mismatch]: Footprint 'JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical' does not match copy in library 'Connector_JST'.
Local override; warning
@(250,0000 mm, 192,0000 mm): Footprint J8
[lib_footprint_mismatch]: Footprint 'JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical' does not match copy in library 'Connector_JST'.
Local override; warning
@(207,5000 mm, 192,0000 mm): Footprint J3
[lib_footprint_mismatch]: Footprint 'JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical' does not match copy in library 'Connector_JST'.
Local override; warning
KiCad V7 also has this same warning, (and it also trows it often), It’s not unique to V8. You have at least tree options to solve it, which I recently mentioned in the thread below:
in my opinion there is actually no remedy to this. I know how to update footprints and effectively, when footprints are updated, the DRC violations are gone. All fine, all good? Of course not. As I wrote in my original message (I hope in an understandable mode, english is not my mother language), as soon as you produce the gerber files all the same DRC violations appear again for the same components and, as a “bonus”, the PCB appears as modified, when this has never occurred in the past.
I repeat again that the footprints are normal stock footprints and not footprints made by me. The only change to them is the reference and the value.
It should not happen. When I fix the footprints they stay fixed.
Next time you correct the footprints and get an error free DRC run, make a copy of the .kicad_pcb file. Then when the errors appear again, check to see if the file differs from the saved copy.
Maybe something in your operating system is reverting to an old version.
I exported all footprints to a new (project specific) library, and also pushed the changes back to the schematic. It seemed that DRC still gave warnings. Then I edited and re-started the schematic and PCB editors, and now I only have warnings for the valves.
And then, after generating a set of Gerber files, all the warnings for the JST connectors are back.
So I seem to be able to confirm the problem, but I am not sure what is really going on under the hood here.
It has changed “roundrect_rratio”, and really, so that the old value seems to be rounded and the new one more exact. In my opinion this shouldn’t happen.
the problem is confirmed and Eelik catched the reason. All JST and Phoenix connectors (why only the connectors?) have the “roundrect_rratio” property altered, from which the reason why, after a plot, the PCB file is marked as modified. Updating the footprints makes those properties back to the previous value, and that’s why at every plot they change again.
I followed the suggestion of retiredfeline and I made two files, before and after, and then compared them. Here they are:
Effectively, this should not happen, but I renew the question: why only the connectors and the other footprints not? Moreover, why a plot makes those changes and only to some footprints?
And I add: can this behaviour affect the final product that I have to send to the manufacturer?
Ah well, I did not look too deep into all the details. I also have not verified eeliks findings, but it looks like there is enough info here to justify a bug report on gitlab. Are you willing / able to make such a bug report?
I’m not sure at all and find it alarming that plotting Gerber files can change the PCB file. This could cause no end of problems for board houses that accept KiCad projects directly
updating the affected footprints after having created the Gerber files and saving, returns the PCB file to its previous state (the affected properties are reverted to their previous values), but are we sure that the Gerber files were created correcly?
