Polygons in pads in KiCad-nightly V5.99 and the Pad edit mode [Solved]

I think I’m having a DRC problem with polygons in Footprints, but I’m not sure what the behavior should be.
This is my simplified situation. A schematic with an RJ45 connector, a spark gap (self made Footprint) and a default resistor as reference:

image

The footprint was first designed in KiCad V5.1.x as two pads, two polygons and a cutout on the solder mask layer.
Then in KiCad-nightly V5.99 I combined each pad with the corresponding polygon into a “group”. In the next screenshot I’ve entered the group in the Footprint Editor:

Then, in the PCB editor (Rebranded from “Pcbnew” in KiCad-nightly V5.99) I placed both the resistor and the sparkgap in between the pins of the RJ45. (This PCB is only for hand soldering at home).

If I now run DRC, it is perfectly happy with the overlapping pads with the RJ45 with both the resistor and the sparkgap, but it chokes on the polygons in the pads of the sparkgap.

image

Both DRC violations are between the RJ45 connector and the Polygons of the spark gap:

** Drc report for /home/paul/projects/kicad/asdf_SparkGap_Polygon_5.99/asdf_SparkGap_Polygon_5.99.kicad_pcb **
** Created on 2021-09-02 00:37:49 **

** Found 2 DRC violations **
[clearance]: Clearance violation (netclass 'Default' clearance 0.2000 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; Severity: error
    @(89.3772 mm, 81.2647 mm): Through hole pad 7 of J1
    @(-0.1250 mm, 0.6000 mm): Polygon on B.Cu
[clearance]: Clearance violation (netclass 'Default' clearance 0.2000 mm; actual 0.0000 mm)
    Rule: netclass 'Default'; Severity: error
    @(91.9172 mm, 82.5347 mm): Through hole pad 8 of J1
    @(0.1250 mm, -0.6000 mm): Polygon on B.Cu

** Found 0 unconnected pads **

** Found 0 Footprint errors **

** End of Report **
  1. Is combining the pad and the polygon into a group the right way to make the complex pads?
  2. Is it reasonable to expect that DRC accepts this? It also accepts the overlapping pads ( Such as between the RJ45 and the resistor).
  3. I suspect it is a simple oversight in the programming, and that the polygon should be accepted as a part of the same net as the pad with which it is grouped.
  4. Maybe these violations could be suppressed with a custom rule, but my gut tells me that it should just be accepted by DRC.

If anybody wants to check if maybe I constructed the sparkgap wrongly, (or confirm I did it right). Here is the project:
asdf_SparkGap_Polygon_5.99.zip (12.0 KB)

In 5.99 custom pads are made in the Pad Edit Mode. Select an existing pad, choose RMB -> Edit Pad as Graphic Shapes. You enter into the Pad Edit Mode. All graphic shapes in the same layer which overlap with the original pad directly or indirectly (the pad and the shapes being part of one continuous outline shape) will be part of the custom pad. Then exit the mode with RMB .> Finish Pad Edit and the pad is formed automatically.

Thank you eelik.
That does work.
I’m still getting to grips with V5.99 and mixed up the pad edit mode with grouping.

Below a screenshot of the differences. Pad 2 is still not modified.
Both only the outline being shown and the bigger pin number look promising.

I updated the test project with the updated footprint, and now the clearance is calculated around all vectors of the pad. DRC is also happy with no violations.

Here the updated example project:
2021-09-02_asdf_SparkGap_Polygon_5.99.zip (12.4 KB)

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