I can’t seem to find anyone having this error. I currently have a copper fill on the top layer connecting all VCC components together. I tried to make a board-wide GND plane, but when I filled it it was also connected to the VCC plane. After creating the plane, kicad gave this error: DRC Outline Error. Not sure what exactly is going on here. Any help would be appreciated.
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That was it. Thank you!
Simpy being on the same layer does not require prioritizing, it’s only when they overlap.
Yes of course on my current board i have 11 different power planes and all of them are 0 priority but dont overlap as i draw them as I want them to look like, not just on the whole board.
So I stand corrected.