When I look at my board at each of the points flagged, I can definitely see that there is a point object there but I can’t locate it on a mask or copper layer to delete it.
In KiCad, normally the solder mask cutouts are the same size as the pads. And If I can still do math:
5.7 / 1000 * 25.4 = 0.14478 mm
which is quite narrow. This is likely to narrow for solder mask fingers to fit between pads, and quite often PCB manufacturers remove these “fingers” silently when they are too narrow. This is usually not a problem as long as there are no copper traces in between the pads. Solder does not wet the PCB, so whether it’s bare PCB or solder mask does not matter much.
You could add aperture masks to the footprints with such narrow pad spacing. Maybe there is a better way to handle this in KiCad (can it be done with custom rules?). I just had a look at the board setup, but I did not see a setting for handling this natively in KiCad. It may be worth a feature request on gitlab, but I’m not sure.
I went through all the flagged areas by HQDFM and, other than these three points and a component that has pad sizes smaller than recommended, addressed them. The new Gerbers were generated, put through HQDFM and these three points aren’t flagged on the new pass.
Two of them were at a location where I had put down a topside copper pad for checking power rail voltages that was resized by KiCAD because of traces too close (and I had missed it) and the third was near two vias that were too close. With these issues fixed, the three “pinholes” are no longer flagged.
So, I’m guessing the three points were artifacts related to the other problems.
How important would that be going back to the original file? Unfortunately, I corrected the problems without saving the original version - sorry, I didn’t think to do that. I do have the original Gerbers if you would like me to upload them.
I don’t get the vibe that this is a potential issue because:
Nobody seems to have reported it before
If I do a search on “HQDFM”, this seems to be the only thread that it’s even mentioned. I’m surprised at that as it’s a pretty good DFM tool to check over your work.
When “real” problems (the resized copper pad and too close vias) were fixed, this error disappeared.
I guess, if it were very important, I could go back and recreate the problems (hopefully the restore change buffer is deep enough) but it would be a few hours of my time. As I said before, I don’t see this as being something that could affect people’s PCBs.
I am not really interested in your files. My interest was more in relation to solving the problem for you. I am still a bit confused between the “Solder mask dams” reported by HQDFM and your remark of “pin holes”. What is the scale of your screenshot? Those 5.7mil, is that from pad to pad, or from pad to dot? (But as before, it does not really matter when you consider it solved).
Another branch of my interest is if whether KiCad can detect and “fix” these thing fingers on the soldermask. It is a very common issue for PCB production and I’m not sure how KiCad handles this. I may look further into this if I’m in the right mood in the coming days.
I do appreciate you wanting to help solve the problem. You’re a great resources.
The screenshot was really zoomed in; the body on the right is the ground pad of a Trinimic Stepper Motor Driver (TMC2209) and the piece on the left is one of the pins.
The distance between them (I just measured on KiCAD’s footprint editor) is 0.16mm or 6.3mil so this is not one of the problem cases.
Just looking what I wrote above and I should say the “pinholes” were about three or four millimeters away from the problem area - I noticed them when I was moving the image in the HQDFM window. I first thought one was a grid point, like you pointed out, I then turned off the grid view and convinced myself it wasn’t a bit of fluff on the screen. Then I searched around the other problem area and found the other two.
Sorry, I should have been more diligent in marking exactly where they were in relation to the identified problem and tried to capture the relevant information. I’ll do better next time.
Let me know if I can help you in any way in your research.
Correct. I have always run a DRC check on a PCB from another tool “just to be sure.” HQDFM was recommended to me by a friend.
It looks like HQDFM is a bit more stringent in the parameters it checks compared to the KiCAD DRC - not a bad thing, especially since this is for a personal project and any mistakes come out of my pocket.
In a broader sense. If you find any class of errors that HQDFM (or other tools) flag and KiCad does not and you consider it would be a useful addition to KiCad, you can consider making a feature request for it on gitlab. If you consider this, then first look whether you can find a similar request on gitlab already (there are around 1500 open issues). If you are in doubt whether a certain feature would be worth implementing, then creating a discussion on this user forum is a better idea. You can compare your thoughts with input from others, and then maybe (or not) create a feature request on gitlab later.
KiCad developers are a scarce resource (and they are doing an amazing job). Lengthy discussions on the user forum are OK, but for gitlab post should be concise, so developers can spend more time on improving code then on reading posts.
It should depend on HQDFM and DRC settings.
The interesting question is: Are there some bugs that HQDFM can detect why DRC can’t, provided you correctly set values of parameters to be checked.
“Smallest Trace Spacing” A couple of pairs of vias as well as a via too close to an SMT pad that I put down that was too close (note the more than 100 other errors here went away when I fixed the ones in the images below):
“Pad size” This seems to be relating to the lower center pad of U4 - This is a TVS diode array that I’ve used in previous designs for USB D+/D- protection and I replaced it with the same part in another package to resolve the issue:
“Drill to Copper” This is the one doesn’t seem to make sense and went away when other conditions were resolved (I changed everything I could before running HQDFM again, so I don’t know what got rid of this issue):
“Holes on SMD Pads” This is a strange one and relates to one of three copper pads I put down (with solder mask apertures) to allow me to easily check power rails (the three pads are +3V3, +5V and GND). When I went back to KiCAD, I noticed that this pad was reduced from what I had originally put down because of a track that was too close - you can see the difference in the solder mask). I moved the track and the pad returned to full size and the error went away.
“Solder Mask Dam” Which are the “pinholes” that started this thread (when I zoom in the hole in HQDFM stays the same size and, as noted in this thread, I can see this as a point on KiCAD as well. This went away when the other issues noted above were resolved - now that when I go back over the other conditions and the steps i took to resolved them, I can’t say which changes “fixed” the problem):
Again, these are conditions flagged by HQDFM that weren’t flagged by KiCAD’s DRC.
Looking back over the six conditions that came up in HQDFM, I would say that 1, 2, 5 and 6 were legitimate catches by HQDFM that were missed by KiCAD. Condition 5 identified something that KiCAD did that I missed in visually scanning the board after updating the fills.
Condition 3, the pad too small, is a judgement/parameter call and while I’ve used the part before, I decided to be safe and find a replacement.
I would label condition 4 as an HQDFM bug. I’m guessing it’s an artifact from the other identified conditions but I spent some time scratching my head over it before moving on and dealing with other problems.
Returning to condition 6 - what I’m calling a “pinhole” did show up on the KiCAD PCB Editor as a point but went away when the other issues were resolved so I really can’t tie it to one or another of the issues identified. I would call this a KiCAD bug - but, as noted above, it went away when other conditions were fixed and nobody has reported this as an issue so I don’t feel it is a significant one.
Reviewing the conditions that HQDFM picked up that KiCAD’s DRC missed, I would say that I was justified in using it as a second check of the Gerbers although I probably spent too much time on the two flagged conditions that went away when I resolved the other ones.
I haven’t done a comprehensive search of this forum and other KiCAD forums but it doesn’t seem like a lot of people do a check of KiCAD’s output with another tool, which I find surprising. I was always taught to get at least on other perspective on a board layout before releasing it to fab.
If something is not perfect because of user did it not perfect I used the word bug (user made bug as he didn’t done it perfectly).
After half year not designing PCB I finished one yesterday but ‘the need for a fundamental change in the project increases as the project approaches the end’. We decided today to make radical change - PCB will be inserted in box upside-down while some parts have to stay as they were (so jump symmetrically at PCB). There are several reasons to finish it today and it is close to 19 here.
So I assume I have no time to check what I write.
I don’t know if KiCad have such check.
I think it should be detected by KiCad.
I have never heard of any limit on pad size and don’t know if such checking can be set in KiCad.
Minimum drill to copper is checked by DRC, I think.
I think it can be detected by DRC.
I don’t understand the term, but looking at picture this condition is in my opinion ‘not possible’. Since 90s I use 3 mils solder mask extension while I use 8 mils minimum copper distance. Recently sometimes I use little less then 3mils and little less than 8 mils but they are all the time far from one to the other.
So for me it looks that only 1. may be is out of reach for DRC. But I’m not sure here.
I have never used any other tool than integrated DRC in used by me design program (97-2017 it was Protel 3, and since 2017 it is KiCad).
Best I know “Sharp corners” is mostly a very stubborn myth, unless your signals are into the multiple GHz range.
I have seen 5.7mill more in this thread. I guess KiCad’s design rules are set to a smaller value and that is the reason KiCad did not flag a bunch of these things.
Minimum pad size…
That may be worth something. 0.3mm is also quite small for pads, but for some footprints (such as BGA’s) pad’s have to be smaller then that. But overall, when designing a footprint, pad placement and size is the most important thing and is not likely to be overlooked or taken lightly.
KiCad does have: PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to hole clearance
Holes in SMT pads. That’s a good one. Some footprints (marked as SMT in KiCad) have THT pads too, for example the shield of USB connectors. It can also be intentional, for example to strengthen mechanical pads of connectors.
“Solder Mask Dam”. Another good one. This is likely worth a feature request, and it has multiple consequences. Simplest is simple detection, a step further is a method to remove these. Maybe in the fabrication output (similar to subtract soldermask from silkscreen. At the moment it could be tweaked by setting solder mask expansion in footprints. Another issue here is that PCB manufacturers do all kind of weird things with solder mask expansion (and also for solder stencil apertures). Because PCB fabs tend to mess with the soldermask it’s hard to predict when copper from other nets would get exposed because of solder mask expansion.
I lack the experience / insight to have a clear view of what to do with these things. (also a bit fuzzy again unfortunately).
HQDFM is configured with production by nextPCB in mind and they want to be on the safe ( as in: high yield) side.
The software is buggy, warning about artifacts that do not really exist (see condition 4 in @mykepredko’s post).
BTW: The parameters are configurable.
