PCBWay : Minimum SMT Width

[itsko]

Question

Is it bad design to alter the manufacturer-recommended VQFN footprint as follows:
• Pin copper width: 0.2 [mm] → 0.3 [mm]
• Pin copper to copper spacing: 0.2 [mm] → 0.1 [mm]

I hate the lack of margins, but my back has come up against a wall.

Also:

Is it common that standardized IC packages with many pins (QFN, BGA, etcetera) are not be able to achieve standard pricing with a PCB manufacturer?

Background

• Package: VQFN

I want to manufacturer a board with a VQFN package.

The package pins have:

• Pin copper width: 0.2 [mm]
• Pin copper to copper spacing: 0.2 [mm]

• PCB Manufacturer: PCBWay

PCBWay’s capabilities specify SMT pin copper width as:

Normal cost ≥ 12 [mil] = 0.30 [mm]
Medium cost ≥ 09 [mil] = 0.23 [mm]
High cost ≤ 09 [mil]

• IPC-2221B

IPC-2221B specifies minimum copper spacing (under 15 [V] ) as 0.1 [mm]:

• Package: BGA

The IC has an alternative package as a BGA, but:

• It is not compliant, like VQFN
  • Copper pad width/spacing is better remedied than VQFN, after alteration (shown below)
  • Via pad diameter appears to make this impossible (shown below).
• It is costlier
• The thermal properties are significantly worse due to the smaller package size.

After pin copper width/spacing alterations, the copper to copper spacing is much better than the VQFN:
• Pin center to center: 0.50 [mm]
• Pin copper width: 0.25 [mm] → 0.30 [mm]
• Pin copper to copper spacing: 0.25 [mm] → 0.20 [mm]

BGA will ultimately require Via In Pad to trace the inner pins past the outer pins.

PCBWay’s associated capabilities here are:

Drill diameter minimum : 0.20 [mm] ( @ board thickness ≤ 1.6 [mm] )
Minimum weld ring (outer layer) : 5 [mil] = 0.1270 [mm] (@ Cu Thick : 35 [µm] = 1 [oz/ft^2] )
Thus:
Minimum via pad diameter = (0.20 + 2 • 0.127) [mm] = 0.454 [mm]

This leaves (0.500 - 0.454) [mm] = 0.046 [mm] between copper pads, at best.
Unfortunately, this is also not compliant and BGA is therefore not an option.

[3Dogs]

Why do you want to do this?
Just use the recommended footprint, and let PCBway handle any over-etching.

[itsko]

Standard difficulty board: $10
Medium difficulty board: $34

That’s very significant at quantity.

[hmk]

Does the cost relate only to the copper width? Is the spacing / clearance between copper not included in the constraints for the cost levels?

[itsko]

My original question to the PCB manufacturer was:

• Define: SMT Width

What does SMT Width refer to?

• SMT package pin copper width?
• SMT package pin copper to copper spacing?
• Something else?

Their response was:

For SMT Width, it refers to the width of IC pads for smt component.

.

I’m now asking here because ignoring spacing feels … dubious.

[3Dogs]

They also have a minimum track width and spacing requirement. I would suspect that a 4mil pad spacing is going to run afoul of that rule.

But, why don’t you just grow the pads and submit the gerbers, and see if they flag it?

[itsko]

Can I do that without a paid submission? I assumed inspections wouldn’t happen until the bill cleared. Thank you very much.

[3Dogs]

Yes, you don’t pay until the job is approved.

[itsko]

They also have a minimum track width and spacing requirement. I would suspect that a 4mil pad spacing is going to run afoul of that rule.

Excellent point about the spacing.

Incorporating this, my original post thus becomes limited to:
• Pin copper width: 0.20 [mm] → 0.25 [mm]
• Pin copper to copper spacing: 0.20 [mm] → 0.15 [mm]

or:

• Pin copper width: 0.20 [mm] → 0.27 [mm]
• Pin copper to copper spacing: 0.20 [mm] → 0.13 [mm]
(Eesh.)

For convenience:
4 [mil] ~ 0.10 [mm]
5 [mil] ~ 0.13 [mm]
6 [mil] ~ 0.15 [mm]
(Note: PCBWay capabilities round [mil] to [mm] conversions to 2 decimal places. The above is consistent with this.)

.

I’ll work on a test run and report back.

[Piotr]

@itsko

• Pin copper to copper spacing: 0.2 [mm] → 0.1 [mm]

I hate the lack of margins, but my back has come up against a wall.

I think 0.1mm is not a margin but below margin.
For many years I was using:
solder mask expansion = 0.075mm and
solder mask minimum web width = 0.075mm.
So the minimum pad to pad spacing was 0.225mm.
The effect was that for 0.4mm pitch I had common mask opening for all pads at one IC side.
But recently I agreed with my contract manufacturer (he asked PCB manufacturer he uses) that they’ll be fine with expansion = 0.065mm and web width = 0.07mm. So I am using it as I think it is better to have mask web between pads than not to have.
But with 0.1mm I don’t imagine now it being possible so from my point of view it is bad design to change copper spacing from 0.2 to 0.1mm

[glenenglish]

So…This is really an EEVBLOG question and is not a KICAD layout question. however.

It depends , to some degree , who wrote this at the manufacturer and their expectation or assumption of your board technology. Some manufacturers assume you will use absolutely high end clearance limits and plugged via in pad etc.
The VQFN suggestion from the MFR looks about right, middle of the road and OK .
0.4mm VQFNs are more difficult to successfully stencil, you will need a 0.1mm thick stencil and T4 paste.
You need to have pad size around pin-land size, and you want some mask in between. and be sure to round the pads corners a bit this reduces stresses and potential for solder balls to become detached.
You will need trace/space 0.15mm to meet a QFN requirement.
JLCPCB dont charge anymore for that I think 0.15 is their standard.

The BGA- providing you have your stencilling sorted (0.1mm thick, T4 paste, registration better than 0.05mm) that package might actually be easier- but you wont know if it soldered correctly without XRAY. Have you got Xray? I do and I would not do these packages without x ray, but that’s because I make 10s of these, not singles…
The thermal properties are not worse due to package size- because the QFN has a big thermal pad on it !
If this sort of geometry is new to you I would avoid a 0.5mm BGA .
why ?

• the stencilling processing is far more rigorous when the ball count grows.
• you will likely need via in pad to route the inner balls, or something like 0.075mm/track space depending on how many layers you have and what signals you want to escape.
  To use these packages, I think you need to adjust your expections and re-evaluate your strategy.

I’d choose the VQFN any day. Why ? You can inspect it. Be sure to follow recommendation for stencilling the big pad, break it up into say 9 of equal spaced 1x1mm apertures. that’s all it will need.

Advice- you must be ruthless on discarding imperfect stencil prints with 0.4, 0.5 features (QFN, BGA) .