I’m scratching my head a bit here. Sure you can roll your own netlist, though you’ll still have to create footprints too…
What kind of circuit design are you involved in that wouldn’t benefit from having a schematic in front of you? How will you share your design with others without a schematic? What record will you have of what parts must be used for each footprint or vice versa?
I understand the desire to stay away from the mouse (vim user here!) and Eeschema and Pcbnew can both be nearly 100% controlled via keyboard, but I think you’re throwing away a pretty useful tool here (schematic editors in general).
I do draw any circuits I design, but depending on size, complexity and application, I do this in different ways. Sometimes I grab a piece of paper and a pencil, and that’s perfectly good enough to build a vero board-like prototype I can power up to do whatever debugging. Sometimes I’m interested in running a bit of simulation, in which case I use a schematics capture tool to draw what I already have in paper. Often times, that schematic is again good enough to serve as my reference for the design (and because of this, I could do with a script to translate netlists across, I favour LTSpice for simulation).
As an electronics designer, I’ve worked in close collaboration with PCB offices in different companies throughout the years, but I’ve never done PCB design myself as a professional. As an enthusiast, I don’t really need a professional grade tool with stuff like configuration control, back annotation and so on, so the risk of my schematics not matching my PCB artwork is acceptable and, because of that, I can have my schematics in paper, or done using whatever other tool.
Maybe it is only tradition that the schematic is drawn. I rarely draw diagrams for software, and in general software is solely text based. The spatial positions of symbols is not fundamental, the interconnections are. So I think it is an interesting idea to write a schematic like one might write code.
I do find drawing the schematic quite tedious, there is a lot of drafting work not related to the actual electronic design. Wires should really rubber band and snap to connection points, rather than be treated as separate bit of graphics. Visio had that years ago.
The spatial layout of the PCB is fundamental of course, copper tracks must physically align with component leads.
I totally, absolutely need to have a drawing in front of me whenever I’m designing I need a structural representation of what I have in mind, shown in a way that is logical in terms of “explaining” what the thing is meant to do But, most often, pencil and paper will do just fine for me. Then again, I do mostly analogue, mixed signal, and power, maybe digital guys can do without I guess?
I have loaded the netlist provided by @Joan_Sparky on my text editor, and it looks very friendly. I was expecting some ugly XML requiring lots of lines and text. It’s pretty meaningful and intuitive.
pcbnew refuses to load it, complaining about “SOTx”, but that’s a different story and one for me to deal with.
Netlist Centric designs are uncommon, but not rare.
Some users find working from PART and CONNECTION ASCII lists easier than managing the custom schematic.
If you look at that supplied netlist, it has some hard library paths included.
You should generate a similar, simple netlist on your own system, and check that imports OK into PCBnew.
That will have the library paths known and aligned for your system.
Then, use your editor to ‘throw stuff overboard’ until it stops working. That gives you a minimal-net format as a base.
LTSpice can export a great many netlists & wirelists, create some, and check which are nearest to your needs,
LTSpice also has an ASCII main file format, so you could look at scripts that read both the main file and the LTSPice.NET, if you want a complete information set.
eg Try Accel net, as quite similar, and the .ASC file has mfg= and pn= string info, if you want to tag more BOM info into LTSpice.
KiCad SCH can also generate LTSpice netlists, and launch LTSpice, so you could trial that too, as time allows.
Oh. Wow. What a great idea. I didn’t even think of this. Using the schematic is so cumbersome. I will also investigate the format and may try this myself!
After all, you already use Verilog and such languages to design digital circuits. All I do in the schematics usually is put down a bunch of components, label them to make connections. This could be done much more quickly and clearly in a text editor.
You might also look at PHDL which is an HDL for creating schematic netlists. The project doesn’t look active, but possibly it has some ideas that are useful.
NETLISTs can be quite powerful, and they are something CAD designers should look to improve.
I’m sure KiCad can borrow this idea.
Taking the PADS ASCII Netlist, as one example
This is a minimal version : (CON-SIP-10P must exist in the library set) PART
J1 CON-SIP-10P
J2 CON-SIP-10P
NET SIGNAL GND
J1.3
J1.2 SIGNAL SomeNetName
J2.2
J1.9
but (not well documented ) is that this is also a valid NETLIST, for new imports.
(If J1,J2 already exist, and second import will skip PART addition)
PART
J1 CON-SIP-10P,Value@Footprint X Y R U M
J2 CON-SIP-10P,Value2@Footprint2 X2 Y2 R2 U M
This allows also assign of Value field, and a re-map of a default footprint, plus an initial placement /rotation, with M field even selecting PCB side.
One possible use of this, is to ‘seed’ the initial PCB placement with the schematic location, as often related parts are close together on the SCH.
I can see this appealing to someone with HDL Centric design flows already in place. Could work well with CPLDs/FPGAs
"The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool."
Looks like adding KiCad netlist would not be too hard ? KiCad is mentioned in the mailing lists chatter.
That’s the whole project - I made it a couple of days ago to test/troubleshoot BOM generation and my python install: Test.zip (11.2 KB)
(the libraries to run these are my own, it’s not based on anything you can get from KiCAD/github)
“SOTx” would be my footprint library that contains all SOT footprints.
That would be possible with some simple house-keeping -
ie avoid using the same Ref’s for Analog vs FPGA, avoid automatic-net names, & take care to match where it matters (3v3).
Most CAD tools allow NETLIST ‘OR’ operations, where multiple netlists can be imported/merged into one PCB.
Revisions can get a little trickier with that flow, as some vary behaviour on First vs Subsequent imports.
KiCad looks better than PADS in that aspect - in the test I just did, kiCad allows rename net by Import & even managed a fractional import
Clearing component “J9:/5080DB5C” pin “2” net name.
Changing component “J9:/5080DB5C” pin “5” net name from “NJ9B” to “NJ9C”.
Changing component “J9:/5080DB5C” pin “9” net name from “NJ9B” to “NJ9C”.
(Here J9.2 was NJ9B, but not present in revised NJ9C netlist)
Like you, I want to use a text editor as well. A schematic-specific language would still be text-based and editable with a text editor. But it would also be able to do error checking, support hierarchy, and allow easy refactoring of the circuitry. Just editing the netlist doesn’t. It’s like the difference between writing machine code or writing Python. The main advantage of editing the netlist is you can do that right now.
The advantage of a hybrid method. Make the root PHDL and allow sub modules that are actually schematic pages. It would have to be that way round due to the impracticality of hierarchical sheets with very high numbers of connections
Cross probing still works, either pulling up a schematic sheet or highlighting the PHDL line
I need a structural representation of what I have in mind, shown in a way that is logical in terms of “explaining” what the thing is meant to do 
But, most often, pencil and paper will do just fine for me. Then again, I do mostly analogue, mixed signal, and power, maybe digital guys can do without I guess?
) is that this is also a valid NETLIST, for new imports.