Pcbnew: How to do Vcc signal with different track widths and clearances along the board?

Hello,

I’m doing a layout for a MCU board.
I have Vcc at 3.3V which supplies the whole board.
To connect this signal to the fine pitch MCU, I need the track to be 10mils and have a clearance of 8 mils maximum.
However, the same signal needs to power more current consumption components and the track needs to be thicker (20mils) and have a bigger clearance (12mils).
I know that I can do it manually, but that way I cannot work with smart features and the DRC will always complain.

I would like to know what are your approaches to this problem or if there is a way to handle it.

Thanks!

I don’t know of a way to have different trace/space limits for the same
net on a PCB, so you can quit reading now if that’s what you need.

If I needed to do that, I would just create separate high-current and
low-current nets and then connect them together somewhere with a
zero-ohm resistor.

In many cases, you’ll want to keep the noise on the high-current net
from being injected into the low-current net (where it might upset your
MCU). If so, you can replace the zero-ohm resistor with a SMD ferrite
bead that will filter out the current impulses.

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Hello,

I am having the same problem. My 3.3V trace width is too wide for a fine-pitch sensor that I am using, so when I try to connect the net to the pad, it doesn’t allow the connection to be made. Has anyone found a solution for this?

Change the track width of the last segment.

Route the wide trace as close as you can get it and double click to end routing. Start a new trace where the previous one ended, reduce the track width and connect the last few mm to the pad.

For this to work, you should have a few custom trace widths set in ‘global design rules’.

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Perfect thank you madworm

I ended up doing this: creating a random line outside of the board footprint I was using (which defaulted as the thinner line (not the 3.3V net width)). Then I used my mouse to box in the random line I had just made and dragged it to the place where I needed the line. This connected the two spots!

I’ve connected the pads with smaller traces, but when I use the design rule checker, it plops arrows on all the areas where the clearance for the pads overlap. Is there a way to change the clearance for individual pads and not the nets they are associated with?

You can change these values per pad. Either in the footprint editor or by mousing over a pad and pressing ‘e’ (“Local Clearance and Settings” tab).

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Great thank you madworm

What is the auto neckdown that I have seen. Thought that was what it was for?

I would like to warm up this topic, form the perspective of autorouting .

I created an own small shcematic component (together with a footprint) to devide segments of the same net, to allow defining multiple track widths per net. Also defined multiple ground and supply components. However I have problems using it, because it makes the schematic ugly (if applied in full depth) and it also requires compromises on the PCB.
High and low current traces of the net are connected only at a single location (causing unnecessary long traces) or I have to define several separate ground and power parts. These segments will also fail to join the copper pours.

While it is easy to handle this problem with manual routing, throw me to the squirrels, I still enjoy Freerouter and it is also better than me.

It would be interesting to have the possibility to assign a separate net class for segments of nets.

As a relatively fresh user of KiCAD and a first time poster here, I also would like to express my gratitude to all the contributors of this great tool.


I have the above design rules, I am trying to implement your suggestion of splitting the track and connecting it with a smaller track.

The track on the left side belongs to the RFAxis Tx track rule.

The pad is 0.7mm by 0.25mm

I am unable to draw a smaller trace of 0.25mm to connect to the wider track. The new small sized track starts but doesn’t move beyond the edge of the wider track.

However I was able to do it in another leg of the same chip, I don’t really recollect how I did it.

Can you advise what is preventing me from doing it.

I noticed that the custom track width option works only in Open GL mode in Linux, is this how it is supposed to be?

Yes. In legacy mode you have to define a range of track widths

I have figured out the problem, I had to reduce the clearance of the wider track to match that of the smaller track while drawing the wider track and then change the clearance of the wider track to my required value. If I draw the wider track with a larger clearance initially then the smaller track doesn’t gets drawn.

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I pretty much did exactly what you’re talking about last night.

I probably had the wrong approach, It did some things that were not unexpected, but were unnecessary as you can see from the tracing here:

The GND pin of P1 is actually just a signal ground (it takes 5V TTL to turn on the MOSFET, which then drains a 12V device at 400mA)

Here’s my design rules:

What you could probably do is have a 0-ohm resistor or some other “null” device that allows you to span from a thicker bus to having a wire or a smaller lead, you just need to manipulate the nets and the rules.

Hope that helps!