I am in a position where I have a relatively thick PCB (3mm) and 3oz copper. Such a PCB needs to carry low current (50Arms) but also some low speed signals (50MHz) - sigma-delta ADC’s
Track impedance is relatively trivial to realise since there is only a dozen of signal’s with two “high speed” layers allocated and I have almost 15mm of space between the area allocated to route power.
To mitigate cross-talk however… I require almost 1mm of separation between such traces. While I have the space to realise this, such space does not exist at the associated signal connector (2mm pads) and the associated IC (~0.6mm SOIC8 ).
now v6 has some really interesting constraints and also potentially an improvement to net-ties so this might become easier to manage going forward, but how to accomplish in v5.1.6?
Option #1 - set net classes low and be mindful of routing, including guard 0V traces between.
Viable but prone to oversight
Option #2 - use net-ties to create a completely new netname so a dedicated netclass
present net ties are “parts” on the outer layer, likewise would require a number of these parts
Option #3 - double up on the SSR and use these to isolate the nets
SSR are already used to control the impedance and edges. Adding more is trivial but a questionable BOM entry
Option #4 - put the constrains in and ignore the violations/override close to the connector/IC
Option #5 - TBD
At the moment I am considering Option #1 but is there any other option with v5.1.6?
Version: (5.1.6)-1, release build
libcurl/7.66.0 OpenSSL/1.1.1d (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.1.1) nghttp2/1.39.2
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
OpenCASCADE Community Edition: 6.9.1
Compiler: GCC 9.2.0 with C++ ABI 1013