PCB Feedback - LT8612EUDE 12V Regulator

Hi all! Apologies if I have misunderstood this category but I was looking for some feedback on the following.
I am very rusty on board design and would greatly appreciate any feedback or criticism!

Datasheet
https://www.analog.com/media/en/technical-documentation/data-sheets/lt8612.pdf

Design

Cheers in advance!
Alex

Strictly speaking, (typing?) this forum is for the KiCad software itself, and not for electronics design or PCB reviews, (There are better sites for that) but there is some overlap and we don’t want to be too picky.

I had a short peek at your screenshots and it looks quite decent, and the PCB layout is also pretty much like the recommendation in the datasheet.

In the datasheet they recommend 10uF for C1, while you have “only” 4u7. The capacity of ceramic capacitors also gets smaller at higher voltages.

That is called the “hot loop” and is a good magic word to find more background info. In the datasheet pins 8 through 14 are all connected to a solid GND plane. Especially pins 8 though 9 are not connected directly to the pad under the IC and this makes this “hot loop” a bit bigger then it could be.

The inductor could also be place a bit closer to the IC, but this is less important because the current though the inductor does not change nearly as quickly and therefore generates much less noise on it’s own.

Remove the zone around the feedback parts (R1, R2, C3) Less capacitance is better here, especially with such high values for the feedback resistors.

You have a few overlapping courtyards. This could be a manufacturing problem (And KiCad usually flags these during DRC).

You have 47uF for C4 and C5. Can they really cram that much capacitance in a ceramic capacitor these days? Gosh…

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Thank you so much Paul for all your feedback, I am consistently impressed and touched by how much people are willing to help!

I have removed thermal reliefs on the IC pads to minimise the hot loop (also thank you kindly for pointing me in the correct direction for further reading!)

I had neglected to actually make sure that components EXISTED in the packages I was intending on using, a very rookie error haha

I’ve found the C3216X5R1E476M160AC which provides 47uF/25VDC in a 1206 package which I believe is suitable for this application and have updated footprints to match. I will confirm C1 is available also and change as required :slight_smile:

I have also removed the zones around the feedback components, it is still not intuitive to me where thinner traces are better than zones - further readying is necessary!

Thank you again, I really appreciate it!

I would use few times more vias connecting GND fill at top and bottom.
Vias near GND THT pads are not needed (connection is done via the pad) but the far end of fills (near the PCB edge) I would connect. I don’t have strong argument for it except that according to my feel such not connected and of two paralel plates can be a slot antenna emitting what DCDC working puts into it.

Here is how I did DCDC converter at my PCB.

DCDC
I’m not sure if my way of routing the feedback track (long way in some distance from jumping L pad and shielded with GND track) is the best one but my main assumption is a continuous GND fill at bottom (I don’t accept even a short brakes). If I route it short breaking a bottom GND than fast switching currents would crossing that break so return current would have to find a longer way than when I have continuous GND and I assume it would be worse.

But the voltage jumping up and down is also a source of radiation so the bigger copper area jumping the stroneg emission, I think.

That design seems to be EOL.

Other than that, the PCB looks good IMO. Some minor suggestions:

  • It could be made way more compact of course with all the large empty spaces.
  • The courtyard of the top right mounting hole is shifted, but this is probably not a problem other than looking stupid.
  • And I’d place some more stitching vias, especially surrounding high current line, like your voltage input in the left and everywhere else where the top GND plane is broken by other traces.
  • Speaking of that, I don’t really like the trace going to the Vout test point, it’s reducing the cross section of the top GND plane a lot. While probably overkill, I’d add a few stitching vias on both sides of that trace so the current can route around it on the bottom side.

I would have reversed the polarity on the Vin connector so as not to cut the GND and with the possibility of making a bigger track for the Vin +.

And maybe being able to trace Vin + also B.CU .

Otherwise it seems OK .

Thank you all for your valuable time and insights, I have actioned most of these suggestions and will be sourcing parts today!

I’ve had to move to a larger inductor, and have restructured slightly to accommodate for it.
Hopefully I haven’t introduced any additional issues! Parts are ordered :slight_smile:


Thanks again everyone!

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I noticed that the clearance between SW and GND at your previous pictures was bigger than now. During switching C between SW and GND is reloaded adding spikes to current pulses increasing high frequency contents in current pulses and increasing power loss.
As you can see at my picture, I tried to not have GND close to switching net (including L end badges that are under it). But I didn’t decided to have a hole in GND fill at bottom. I think it can be done if you have the whole device shielded and my is not. Bottom is 1.5mm away from switching net.
The capacitance between adjacent tracks is not high, even when they are close so may be my solutions at top are going too far if at the same time I have full GND at bottom…
Edit.
I found that small clearance I noticed is not to GND but to second L end but it makes no difference. The second L end is not switching DC so in that case is the same as GND.
In my opinion there is reason to have opening in GND fill at bottom under switching L pad, but there is no reason to have it under DC L pad.
And one more…
C4 and C5 in my opinion should have wider thermal connections at their 1 pads.
And, if I correctly understand 5A then thermal connections at output also seems too narrow.

What happened here?
grafik

There are two holes in the copper fill below pad 2 of C5 and the clearance around the 1 pads is relatively small and there’s a weird “step” in the clearance below C5 pad 1.

Zone clearance?
Top of pad 2 R2 is the same.
Compare to clearance on R1 both pads.

According to oblique lines I see under C5 pad 1 I suppose there are two GND fills. One with small clearance and second with bigger clearance and bigger thermal clearance. That explains both what you noticed.

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Yes you are completely correct, something I missed when updating the footprints!

I will note the above changes as future work as I have ordered the boards and will do a test build in January.

Thank you again so much people - your time, input, and expertise are greatly appreciated!

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