PCB Editor, DRC doesn't see silkscreen on pads?

Layout
1

Hello,
I’m updating an old project on 7.0.1, ran DRC, and got no error reported for this:
Capture d’écran_2023-03-24_16-06-02
The top silkscreen ref designator “U1” in blue is clearly over a TH pad.
(same for the value text)
Any suggestion?
Thanks!

2

Any and/or all DRC messages can be suppressed. The setting is in: PCB Editor / File / Board Setup / Design Rules / Violation Severity.

3

@dhaillant You are right. Looks like a bug or rather a missing feature. No violations set to ignore.

[EDIT] There is not even an entry for that in the severity matrix. The setup constraint “Minimum item clearance” seemingly only covers silk-to-silk, not silk-to-pad/via.

I did not notice that as I have a check in my custom defined rules

#make sure silkscreen text does not overlap vias or pads
(rule silk2via
 (constraint silk_clearance(min 0.15mm))
 (condition "((A.Type=='*Text') || (A.Type=='Graphic*')) && (( B.Type=='Via' ) || ( B.Type=='Pad' ))"))
4

The top silkscreen ref designator “U1” in blue is clearly over a TH pad. Any suggestion?

Looks like a bug, the DRC-test “Readability → Silkscreen clipped by soldermask” seems not to work.

5

Agreed, please raise an issue

6

done. sorry, forget the link:

3 Likes
7

Try todays Testing build. There is a commit to fix this

9

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