Fab layer is a technical layer.
Meaning it has no influence on the pcb production.
Only as an aide for assembly process.
That’s why it’s called assembly drawing in other tools but kicad.
The stroked lines in the center of the drawing in that datasheet depict symmetry lines (usually dot-line-dot-line), which tell you that everything right/left or over/below is symetrical to them. They’ve drawn them for the device only, but from the pin symmetry you can glean that the pads should be symmetrical as well, so you can align both to a common center… not 100% nice and complete, but will do. As one can see, there is worse out there (looks at Omron FPC).
Mistakes you made with your footprint:
- the pads centers are placed wrong by 0.1 mm each direction…
- you enlarged the pads by 0.2 mm (they are already big to begin with) - why?
- housing outline on F.Fab is 0.1 mm too short
- courtyard is asymmetric to center for both vertical and horizontal
- F.Silk is asymmetric to both vertical and horizontal too
Some other things:
- housing width on F.Fab could be smaller than what the pins stick out, but that’s personal taste
- the pin 1 marker on F.Fab can go right on top of pad 1, no need to sit aside, better yet put it at the corner of the housing as that is what will be present on the real life device
- your silkscreen misses a pin 1 marker, and this device is polarized as the crystal is only between pin 1 and 4, so after/during placement it’s good to have a reference (as you already did go thrghou the troulbe of having a silkscreen for the part, might as well go the full mile)
- reference fields can go over the courtyard (no need to be so far away), the silkscreen one just shouldn’t go over pads that need to be free for soldering
- your courtyard had 2 extra lines that where obsolete (clean up missing)
- you had a little lapse with the silkscreen near pin 1, the endpoints are not sitting atop each other (important for Edge.Cuts to be that pedantic, not a problem here)
- unless you have a good reason not to do this, pin 1 should be at top left
- it should be safer to define the adhesive pad with a SMD pad on the adhesive layer only
As for silkscreen line width, refer to the specs available from your boardhouse of choice… 0.15 mm is smallest that’s at no extra cost usually.
Text height - depends on you and your eyesight. 1 mm is pretty darn small if you ask me, but usually still readable. Stuff get’s smaller all the time… just look at 0402. In the hobby area people still work with through hole components, so can go big with the silkscreen as well if they need it. Really your call.
Crystal_7.9x3.7_SMD.kicad_mod (2.7 KB)
PS: I don’t use circles on silkscreen and fab layer anymore as I had cases where they didn’t appear on the finished pcb… I use lines where ever possible or at max arcs, those are supported.
PPS: I would have called that footprint either by the manufacturer ID or at least by it’s outside dimension, as your current description isn’t very distinguishable if you get another 4 pad SMD crystal 
2 Likes
I probably don’t depict the pins in the fabrication outline, as I use my 3D models to check that the footprint is OK and the pads are at the correct positions to match the device…
So I can follow why @nicholas does draw the pins when he does the device on the fab layer.
[Sort_Of_Off_Topic_Comment]
It’s sexy to hear somebody speak “drafting”! I never mastered that language. The administrators in my High School STRONGLY advised me to take Latin, or Spanish, or Philosophy, or Logic, rather than Drafting. (And I got into trouble when I attempted to do an end-run around their restrictions, but that’s a story for another time.)
In college, a short survey course on drafting and drawing control systems was required as part of the Engineering core, but that requirement seems to have been dropped quite a few years ago. I continue to find instances where even my pidgin-level comprehension of the drafting language seems to be an appropriate and efficient method of communicating a thought or information, but it invariably falls on deaf ears.
Thank you for taking the time to give that short lesson!
[/Sort_Of_Off_Topic_Comment]
@Nick123, @nicholas, @Andy_P, @Joan_Sparky, and everybody else who has contributed to this thread:
Thank You Very Much for your comments! I’m still going through all of them, understanding your methods and workflows, etc.
Just want you to all know I appreciate your time & effort.
Dale
3 Likes
[to stay off topic] 
In all honesty… I never learned that language myself - I wish I had, but my educational career didn’t entail engineering drawing, though I probably could have sit in lectures about it when I think about it.
I don’t know (or really care) what that little crossed cone on drawings means (sure something about what type of projection one is looking at), I don’t know the symbols for surface lapped, just ground or painted… I have no idea how they mark dimensions that need to be at least as big as something, or have a strict tolerance… etc.pp.
So, all I do and that comes from me is more or less self taught with a lot of learning-by-doing and reading other peoples thoughts or ramblings on matters.
I never felt good at being a specialist at something… I’m more a jack of all trades guy, that does some things good and some bad and always strives for best 
[end off topic]
Thank you so much Joan
your 4 yellow lines on the F.Fab one yellow line segment properties are
start X = -1.75
end X = -1.75
start Y = 3.95
End Y = -3.95
making the length of the line 7.9 mm did you follow any datasheet for that or it is just an estimated line
Regards
Check the datasheet for that crystal… it’s long side is 7.9 mm +/- 0.1 mm.
I usually take the center value if the tolerance is symmetrical, otherwise I calculate a new value that sit’s in the middle between the two extremes.
The fabrication outline of the device is for you during layout and for someone else later who needs to find the device on your board, either for repairs or assembly…
So it should be accurate, but stick with the average dimensions, not the extremes.
The courtyard is on average 0.25 mm larger than that and will take care of the extremes, depending on device size etc… I don’t know the industry standards as I’m not a layouter by trade. I remember the Rheingold Heavy website I linked to further up has got some more values for different scenarios if you need them.
PS: call them yellow lines fabrication outline, as on my system those are bright white/yellow, nearly white… people will know what you mean when you say fabrication layer (or assembly layer, as @nicholas is calling it)
ok fabrication line but the other fabrication line is 3.5 mm where is that mentioned in the datasheet
The width of the housing isn’t given… only the outer dimension of the pins… 3.7 mm.
I took artistic liberty and decided that the pins stick 0.1 mm out to the side of the housing, which makes the housing 3.5 mm wide. It’s probably even thinner as usually the pins are made from 0.2-0.3 mm thick metal.
Personal taste, you can go with the 3.7 mm naturally.
- ok also you have added eco1.user label %R what is that for ?
- if i understand correctly %R must be used only for the Fab layer not for the silks screen text/label correct ?
When I do layouts I switch off:
- silkscreen
- references
- values
As I still need to know what is what in tiny unobtrusive letters, but that also sticks out visually I use the Eco1 layer for references:
left - fab layer references/values visible, right - switched off, devices are 0805 mostly
text size for fab stuff is 0.6x0.6x0.1… imagine this with 1x1x0.15 and silkscreen references!
Using REF** on fab layer allows me to switch off the reference/value text while still being able to see the fab outlines of the devices for placement.
The difference between REF** and %R is, that REF** is switched visible/invisible by the Reference option in the render tab and for the %R it depends on the layer it’s on, like Eco1 or F.Silk for example.
- so this %R on the eco1.user and on the silk screen will be copied from the schematics am i correct? because i got to redo for nearly around 400 components
so want to be careful from the beginning
1 Like
Yes.
%R and REF** read the reference fields from the schematic.
%V or VAL** do the same for the values.
Just in case, copy your project folder (backup) before you import new/changed devices to your layout - when stuff goes wrong.
hi joan
i have done few footprint for few components
https://drive.google.com/open?id=0B1rwVwGpi1IbZUE4NlV1ZGJpOUk
can you please review and let me know your review comments
in the above link there is an excel sheet which has links to the datasheet and its relevant footprint file
- And for any minor cosmetic changes which would not impact my PCB design or fabrication you can ignore such review comments.
2.if you put a review comment then that means it was a error in the footprint drawing and can have a significant impact on PCB design or fabrication process.
your review must be in 2 sections
Error/bug: All major errors in the footprint put under this section along with footprint file name
Cosmetic changes: you may ignore this section but just in case you want to add some info.
Regards
Nick
hello Joan
this one looks bit confusing can you please help with its footprint
datasheet and footprint both attached to this message
the data sheet say the cathode is horizontal 
LED-0603.kicad_mod (1.7 KB)
It looks like a basic 0603 footprint to me, similar to a resistor or capacitor with the same dimensions. Have I missed something?
Of course, silkscreen that covers part of a pad will probably interfere with proper soldering. There is no debate about that. However, there IS active debate about about silkscreen (as well as traces) that falls between the pads of SMT components. Your diode symbol is an example. Some manufacturing engineers claim the cured silkscreen (or copper trace) is thick enough that it can lift the SMT component, prevent the SMT endcap metallization from touching the pad it is intended to contact, and create a bad solder joint. Others claim there is more than enough solder paste placed on SMT pads to fill the gap and create an acceptable solder joint.
This is less likely to be a problem with packages (such as an SMB diode package) where the electrical contact is created by bending a metal lead frame over the end of the component package. In those cases, the actual component body sits above the plane of the electrical contacts by 0.05 mm or so, creating a gap between the board and the component body where you can safely place silkscreen (or a trace).
Dale
dear kicad
can some one pleases make a footprint of the following component this is the SD card Slim type with switch
Regards
can some one please review this footprint
RJ45_TRANSFO.kicad_mod (3.1 KB)
datasheet is in the bellow link
http://www.farnell.com/datasheets/79319.pdf
except the hole size which is 1.016 in my case where the datasheet says 0.89 any other review you can let me know
regards
Dear Kicad
please ignore the previous message of making footprint i shall make it as i can be extra cautious may be i can post the footprint so that some one can review.
also i noticed that many footprints default present in kicad library 9 out of 10 are having incorrect footprint so my suggestion please check all the footprints before sending it to assembly house.
in fact i just had trusted many footprints from kicad library and was about to go with fabrication but Joan_Sparky , nicholas & keruseykaryu and few others helped out thanks a ton to them.
Regards