Attached is a layout I just did, avoiding placing a pad or via directly on a track, along with a different hopefully more clear example. https://postimg.cc/gallery/jyqfgw2i/
I learned this method in vocational school and the teacher told me its done to avoid tearing the track when drilling the THT holes. But he also didn’t want to see it on SMD pads. So I just did what he wanted to see and it was all good.
They’ve got a 20 year old CNC with a .2mm head to machine the PCBs. Only single layer boards are possible. No ground fills as the controller can’t handle thermal reliefs and pours in general. Bridges are allowed (but to be avoided) and done manually with the legs of THT components.
Instead of KiCAD they want us to use Sprint Layout 5.0 which is OK for smaller projects but a nightmare above 20 parts
What I want to say is I’m fine routing like that. But I’m wondering if this is a common/“professional” practice or if it only applies to “DIY” made PCBs and their own unique design rules.
greetings from zhe Germany
dj_ordje
Edit: Yeah I’m aware of the trace between D7, Q3 and K2, fixed it its more straight-forward now
Certainly it’s not professional, and it doesn’t apply even to DIY because everyone can get a board manufactured in China for $2 or something like that. 2 layer board is standard for most hobbyists and all manufacturers do it by default, they even don’t have option for 1 layer board (it’s just a 2 layer board without tracks in the 2nd layer). Using through hole components may be common but even hobbyists can use SMD components, which is IMO more fun and gives more space on board.
You should adapt the PCB design to the technology you use to make the PCB.
With the prices from (mostly Chinese) fabs you can get double sided PCB’s with metallisation, 2 solder masks and 2 silk screens for about the same price as the base material and the postage stamps. (eelik’s reply pops up, he knows too).
When PCB’s are etched you obviously have no trouble with tearing of the copper.
Boards without Ground planes are very bad from an EMC point of view, and if you go into the direction of “professonal PCB design” there are a lot of things you have to think about during PCB layout.
When reflow soldering parts are more likely to tombstone (SMD components only soldered on one side and standing vertical on the board) if one of the pads has more traces than the other, because this causes uneven heating, which results in more time that things can go wrong. For hand soldering it does not matter.
You obviously had to struggle to get the component numbers in the copper layer. These are normally printed on the silkscreen and are placed right on top of the Silkscreen and copper.
The board looks usable for a first board, but it definately designed around a lot of limiting factors for homebrew and milling.
Thanks for all the input! Appreciate it!
But I have to say that that isn’t my first PCB, I’ve ordered something like 5 or 6 different projects from OSHpark over the last few years, growing in complexity and general improving layout strategies (My first ones were made point-to-point without 45° angles or anything close to that )
And yes, this design was made around the above mentioned DIY design rules as it takes two weeks for an OSHpark order to get to germany and I can use the CNC at school whenever I like. Its OK for prototyping but I too prefer two-layer.
I’m familiar with Silkscreen layout and the like, however I didn’t know about the effect the traces going to a pad have on tombstoning, interesting! I will dig deeper into that rabbit hole
Regarding the layout concept of pads on line with traces. I’ve been designing devices for aerospace and automotive for some years. The designs have been analog or mixed signal, some switching power etc. In all cases EMC is of foremost concern both emissions and susceptibility. I would never put a capacitor on the end of a “stick” trace. It almost defeated the purpose of keeping the series inductance to a minimum.
While I realize few folks here are not designing for such applications, there are increasing high frequency designs where lead inductance is not a good thing. Currently there is another post from a user building a class D amplifier. Here high frequency layouts are more critical.
Regarding tombstoning:
Another interesting thing about SMD automatic soldering is the pad shape is critical to the component location. When the solder melts, the surface tension of the solder actually moves the component to the center of the pad (ideally) making for an optimum installation.
If you find a youTube video you can see the parts moving around and aligning themselves…kinda cool.
@Seth_h Will check them out as they are even a bit cheaper than OSH. Also I found this in the Imprint:
No animals were harmed during the production of the AISLER online experience.
@JohnRob I see that I have to do some reading haha
A switching PSU for a 1970s Porsche Ignition box is on the project list so I do in fact need to educate myself in high-frequency/EMC circuit layout…
Are there any Books on that topic that you can recommend?
I would never put a capacitor on the end of a “stick” trace. It almost defeated the purpose of keeping the series inductance to a minimum.
Which is exactly why I always see the small coupling caps directly ON the traces of say an IC or Transistor, makes sense.
Since you mentioned the moving of parts under soldering I have to confess that I’ve done all my soldering including SOT-23 and SOD-123 by hand
However a toaster reflow-oven is on the project list
In addition to keeping capacitor leads short you want to keep the change in current areas small.
You won’t be able to do this on the ignition but on a switching supply (and to some extent the ignition) you want to keep the area of circuit board in which the current changes, to a minimum.
For instance, if you layout a simple buck regulator:
Draw (literally, on a print out) the current path when the switch is ON. Look at the area inside the current path.
Then with the switch OFF, draw the resulting area. These should be as small as practical.
And what area does exists should overlap as much as possible.
These are concepts and to the extent you can accomplish them it will reduce EMI. You cannot however make them perfect.
Another hint regarding switching currents or any “high” current. Via’s have thinner copper in the ID than the trace thickness. To increase the conduction cross section, increase the via hole 0.8mm and the pad to 1.6 mm (or even larger if you have the room). I’ve also used multiple vias for traces I felt needed extra conductivity.
The first link points to http://www.surfacemountprocess.com/design-for-manufacture.html
which has some nice pictures and explanation about some of the design for manufacture motto, and some examples of mistakes made with explanations, so you won’t make the same mistakes if you read it.
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