NOTE: The forum doesn’t seem to like angle brackets, so in the text below, left angle bracket (the less than symbol) is “{“, and similar for “}”.
I am struggling with creating a custom rule to allow me to place unconnected TH pads (or top/bottom vias) on top of unconnected SMD pads. The reason for doing this is to grant SMD components, such as connectors, better rigidity. All too often I’ve had to repair a PCB where the user has been a little too enthusiastic inserting a plug and the (SMD) connector has ripped off the board. Often happens with micro USB connectors, and USB-C connectors. It wasn’t such a problem when connectors had legs that went through the board… but it seems that is becoming a rarity.
To solve this problem I like to put a pad or via on top of the copper land that is supposed to provide mechanical support for a connector, but get DRC clearance errors when doing so.
The connector mechanical “support” pads are {no net} and the pad/via is {no net}, but I can’t figure out a custom rule to ignore such constructs.
What I need is something like…
(rule “Anchors”
(condition “A.NetName == ‘{no net}’ && B.NetName == ‘{no net}’”)
(severity ignore)
)
But it would seem that although {no net} is a valid DRC error (eg: “PTH pad 1 [{no net}] of ”), [no net} itself is not a valid description of a net with no name, and neither is ‘no net’ or ‘‘ (a quoted null).
The normal way to do this is to add THT pad directly in the footprint. And to satisfy KiCad’s DRC rules the pad numbers of both the THT and SMT pads are the same. This is probably done with a bunch of connectors too, but it is very common for the use of thermal vias. Just open the footprint editor and search for the word “thermal”.
You can also use the Preformatted Text button to include “difficult” characters in your text on this forum.
Only for mechanical connection I have pin-header SMD 3 pins at schematic (nothing connected to it). Then I place it at PCB and I place 2 vias at its each pad. I have never used any custom rules. DRC not complains on my solution.
@paulvdh
Thanks for the tip on ‘preformatted text’.
Placing the ‘anchors’ inside the component definition is a solution I have used previously, but it doesn’t always work: in the design I am working on the position of the ‘anchor’ is not in a predictable location across several placements due to clashing components being placed on the reverse side of the board. Hence I place the ‘anchors’ at locations that are offset from where one would normally like them to be… ideally smack-bang in the center of the SMD pad. With unpredictable clashes I sometimes have to move an ‘anchor’ left/right/up/down on a per-pad basis so it does not interfere.
I also tried labelling the TH pad the same number as the SMD pad, but still get an error.
@Piotr
Interesting. I tried the same process, except used the “Micro_SD_card” object from the symbols library and linked it to a “microSD_HC_Hirose_DM3AT-SF-PEJM5” footprint (names given in case anyone wants to replicate). I’m using KiCad 8.0.9 on Ubuntu 20.04.
The footprint has SMD ‘mounting pads’ upon which I place a via.
I get the following DRC error:
Hole clearance violation …
Pad 11 [<no net>] of J1001 on F.Cu
Via [<no net>] on F.Cu - B.Cu
The board I am working with (not the trial I did for Piotr) was imported from Altium (I am SO glad I switched) and I just noticed my ‘anchors’ got brought over as free pads, not vias. However, changing them to vias still gives me a DRC error, but a different error:
Front solder mask aperture bridges items with different nets
Via [<no net>] on Top Layer - Bottom Layer
Pad 0 [<no net>] of CN41 on Top Layer
Interesting, despite saying “items with different nets”, the nets are actually the same!
A question directly related: how do I specify “no net” to the rules evaluator?
