I have a component (J5 on Pmp_Vlv sheet) that I have laid out in my schematic that the net are not correct on the PCB
I have tried everything I can think of short of deleting the PCB and starting over.
Does anyone have an easy fix for this?
Pool.zip (292.9 KB)
gmc
2
Difficult to troubleshoot as you haven’t attached the footprints. Try editing the footprint on the PCB and update footprint from library.
@gmc Changed the footprint to a different 6 pin header in the schematic and the something with the nets.
BobZ
4
Did you do go to tools and select update pcb from schematic?
What KiCad version is this, I am seeing 2021 dates in the files?
After very change I made to correct the issue
Application: KiCad (64-bit)
Version: (6.0.10), release build
Libraries:
wxWidgets 3.2.1
libcurl/7.86.0-DEV Schannel zlib/1.2.13
Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
Date: Dec 19 2022 21:23:04
wxWidgets: 3.2.1 (wchar_t,wx containers)
Boost: 1.80.0
OCC: 7.6.2
Curl: 7.86.0-DEV
ngspice: 38
Compiler: Visual C++ 1929 without C++ ABI
Build settings:
KICAD_USE_OCC=ON
KICAD_SPICE=ON
I found the issue
If you look at the image you will find that I label the nets with net labels instead of just using plain text and apparently net labels have priority.
I removed the labels and the nets returned to the schematic layout.
In 7.0 you can use a “Directive Label” to do labelings like that which will not override the net name.
system
Closed
10
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.