Patterned edge plating

Hello Everybody:
Seen a few youtube videos and other descriptions of how to describe edge plating: and KiCAD does have a place for selecting on the Board Setup page.
But HOW exactly does one see what that selection entails in the “plots”?
What type of drawing will best illustrate edge plating parameters?
Our most likely pcb house will be FLCPCB if that helps.
Any help in the matter will be highly appreciated.

IWith the cheap manufacturers it’s something you have to specify in the web order form (and will cost more).

I’m not sure if I’m answering your question.

When I asked our local PCB manufacturer how to document PCB with some pads at edge I got the info:

  • I should mark in order that PCB has platted edge,
  • then any THT pad that is partially in PCB and partially out of PCB will be platted also at edge.

I just placed THT pads with their hole center at the PCB edge and got plated half holes with some extra plated at PCB edge according to my pad sizes.
I was doing it few years before 2017 when I started to use KiCad so I don’t know what KiCad DRC will say for it :slight_smile:

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There’s a CheckBox for Edge Plating and, you can use Castellated Terminals/THT and set them in the Panel.

You can explore Kicad to find them or, look at other Posts (no need for me to re-post).

Also, can ‘Cheat’ but, how you do it will depend on who is making the PCB and what they Require… Always best to include a Drawing with Details that clearly specify what you want…

Images below shows Castellated Terminals (SMD on Top and Btm Layer) and my Cheat at putting Cu on Edge… (of course, real project would Not link each Terminal to the Edge Cu…)

Thanks a lot for your effort in answering my questions on edge-plating.
We do “castellated” vias on the edge a lot.
But they are too weak to be used as “edge-connector”. We are going to make the PCB assy stand on its edge( with something to hold it upright) and reflow soldered on the main System PCB. So no legacy connectors will be used.Either “too expensive” or too bulky…
It seems that my bigger problem is to create a 3D model using Fusion 360…I do not think it is possible to do this using FreeCAD…I did not succeed in Trial version of Fusion either.
I think PCB fab house has to have a 3D model to see what is being requested.
Hopefully, they can use STP file to extract the true dimensions.

Here’s an (oldish) FAQ article: Castellated edge; plated half holes in board edge

I have visited the problem a couple of times with later versions, this one was originally written for v5. The basics are still the same. Track routing may still be a small problem. Nowadays KiCad has “Castellated pad” fabrication property for pads (and then the checkbox in Board Setup), but it doesn’t help much for board manufacturing process. Basically, if a copper feature goes over the board edge, the manufacturer takes it as a hint that the edge should be plated. But you have to ask or communicate it clearly.

This seems the most likely way to proceed.
Although a 3D model 1:1 will be immensely helpful I think for the pcb mfr.
thnx a lot

What about something like what was achieved in this thread ?

Never mind the previous help question- although remains a mystery.
We had two boards being designed concurrently on one project. So that a part of sch is on one pcb, while the rest is on an adjacent pcb.Sharing the same netlist.
The second one will not do copper pour.
But when we split into separate projects- as the intention was- lo and behold, zones come out filled!.
Maybe it has zones filling process valid for only areas within the boundary of ONE EDGE CUT.
some awareness!: might help others…

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