I’m trying to build the green rectangle for the solder to connect to the thermal pad. I can’t figure out how to get different clearances for the x and y dimension.I was using the solder mask clearance but it seems to apply to both. How can I get different top and side clearances?
Last part of the question is after I make the mask clearance for the green area, should I be breaking up the paste layer into smaller “blobs” so its not just filling the whole green rectangle with solder? Thanks!
For these kind of more complex solder mask and paste openings you have to check off the mask or paste layer from the copper pad and create an independent aperture pad which has only the wanted mask or paste layer.
Indeed. Create a separate pad for this.
But not only that…
Aperture pads are not allowed to have any pad number. I’m not exactly sure about the details. If unsure, then start by having a look at some of the footprints in KiCad’s default libraries. Most of the pads responding to the magic word “thermal” will do.
I am guessing here, but I think the solder mask may interfere with the bottom of the pad.
It may be better to have the solder mask cutout over the full size of the IC, and then only control the amount of solder with the size of the solder paste cutout.
But it’s just a guess, I have no personal experience here.
Despite my ramblings. I looks quite good / usable.
The copper area is larger than the pad because it gives a bit better heat conduction, I guess. But the mask opening shouldn’t be much larger than the pad.
The thermal pad in the IC may be smaller, but the thermal pad on the footprint is full size. Those packages usually are also flat on the bottom.
Result is that the solder mask lifts the IC package.
The stencil cutout limits the amount of solder available for soldering the thermal pad, and it will wick into the 12 exposed via’s.
When the mask cutout is the full size of the IC, then it can settle a bit lower, and less solder is needed to fill the gap beween the thermal pad on the IC and the thermal pad in the Footprint.
It’s a small thing, and I’m not entirely sure how this translates to mass production.
The Thermal pad on the bottom of the IC has the same size as the hole in the solder mask. I don’t know how much soler past will get applied to the board, but it should fill the area below the thermal pad.
That the solder paste can wick into the via’s sounds like a valid concern. But Kicad has a lot of ther footprints that do the same. So that will have to check out. Unfortunately I can’t check it without an X-ray machine.
OTOH the design rule checker (DRC) now goes wild on all the via’s in the thermal pad. So that will needs some figuring out.
I’ll first check the design rules of my supplier and maybe that solves it.
Or can you exclude pieces of a footprint from the DRC?
Edit: I figured it out. The bottom copper had a different pin number than the top part and all the thermal via’s. Found it out by pulling all the stacked pads apart and check the pin numbers.
This should not happen.
You can easily verify by using one of the many footprints with thermal pads in KiCad’s default libraries.
You do have to set the pin number of all these pads to the same “pin number” (Which can be any alpha numeric string upto 4 characters long.
@paulvdh I figured it out. The bottom copper had a different pin number than the top part and all the thermal via’s. Found it out by pulling all the stacked pads apart and check the pin numbers.
