Although there are various commercial Gerber editors to panelize PCB and stencils, the missing pad manipulation and panelize functions seems one of the disadvantages of the Kicad built in Gerber viewer.
Exploring the Architects desktop of our Freecad friends, I came across the “Arch-Nest” algorithm probably intended for things like sheet metal, plasterboard or plywood materials.
what is exactly the panelize functionality to fill any average PCB manufactureres production panel of typically about 400x600mm with diffrent PCBs. Anybody experienced with that Arch desk function ? Seems Python - possible to adapt for invoking this for Kicad PCB panelization ?
Sorry if there are already bug reports in work about this topic.
Bug report about what topic exactly?
KiCad has a Gerber Viewer, and not a Gerber editor. Last time I checked (A year or so ago) there were no plans at all to turn it into a gerber editor, (although some very small gerber editing may be added) and KiCad also has no plans to add support for panelization. There are a few plugins though that can help with panelziation.
Are you wanting to panelize your PCB before sending it to a manufacturer, if so what is the use case?
Manufacturers will add alignment pin holes/fiducial/calibration features to the perimeter of the panel depending on their equipment and tooling. So even if you know the panel size it’s less clear what the useable space will be. That’s why shops prefer to take individual boards and create the panels themselves.
Up on today, we use GT-Designer by wssi.com to do the job by commercial license. There are numerous posts in the Kicad forum about panelize what would be a benefit if supported. Panelize is not usefull if you have only occasionally one design (what is probably most of the Kicad users). I know, the gerber viewer is a viewer what will never change to a gerber editor why its not a bug but a feature. But Kicad is FOSS and FOSS is a labority for new ideas beside the mainstream. This way, dont understand this post as critics. Possibly the panelize is better done on the PCB source level data than Gerber format. On the other hand, Gerber is able to combine our older designs from other ECAD what are Mentors Expedition, Eagle and Altium.
If you have frequently several diffrent low production number prototype pcbs, you might do the job of any PCB pool dealer yourself. This saves a significant amount of setup expenses for each design by lower price per area for each order. Some PCB manufacturers do not like this customers as those designs cuts their profits. Several other manufacturers tell us their prefered panel size, boarder sizes and clearance for milling and offer unbeatable good quotes. They only add fiducial (or use some existing of the pcbs), UL-Logo and sometimes a copper balance pattern to the unused area what is typically <10%. The panels are shipped without milling or pre-milled like a chocolate bar. This is my frequently prefered PCB workflow.
Anybody is free to write a paneliser starting with the (open) specs of the PCB file. Prehaps those of you professional users who care can crowdfund somebody to do that. I doubt that mose people here do.
With miniaturisation many boards fall under the 100x100 (sometimes 150x100) mm threshold. Above that the price rises that you will get little return or even a loss for panelising yourself.
Not some, it’s most of the low cost suppliers.
An issue for panelising is dealing with nets on the different boards with the same name. This breaks board testing if not modified.
