When going through DRC, the checker gives me the error message:
“Padstack is not valid (SMD pad copper and mask layer don’t match)”
Where to look for? My mask layer follows the copper layer 1:1 (solder mask clearance set to 0) but this should just use Board’s general solder mask “expansion” value. So what’s wrong here?
I am not very familiar with that DRC violation, and I guess a screenshot won’t help much, but if you create a little test project with your problematic footprint, then probably several people will be willing to have a look at it.
I think I have it. My footprint is SO-8 with power pad. I wanted to expose bare copper on both Top and Bot layers, while the pads have been on Top only. My footprint have the F.Mask and B.Mask checked for this pad (to expose also Bot copper) and that’s what Kicad complains about.
Probably thinks that having pads on Top and mask opening on Bot makes no sense.
If I leave mask opening only on Top, DRC does not complain. Case closed 
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