Pads on copper pours

I’m laying out a TI power regulator TPS563207.
The recommended layout uses pours on the front to connect certain pads (and I’m guessing heat dissipation).

I started to create the recommended planes but I’d like to know what properties I should be setting on both the pads and the plane. Right now I have them both to “solid” connection, but I have read that when you try to solder to a large copper area you need thermals otherwise its hard to get the solder hot enough. Also for these thermal vias I basically just made normal vias that attach to the ground plane. Is anything else needed when these are located on a pour? Below is the design I have so far, U1 is the regulator chip (the huge pad to the left is the inductor). Thanks!

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I design power electronics and this subject is one which I frequently face. I will almost always favor solid connections to the vias (as opposed to thermal reliefs) because the thermal relief mostly defeats the objective of conducting heat from the IC. Thermal vias with solid connections can work surprisingly well, and of course they also require more heat for soldering. Solid connections are also better for conducting high current which is probably not your issue at hand.

Do you know who will be doing the soldering and how they will be doing it? Good idea to consult with the assembler as the manufacturing engineers should be able to indicate what they can handle.

For a 2 layer board which I will hand solder, I like to use the largest possible through hole pad in the belly pad, and after mounting the chip I poke my soldering iron tip into the hole from the back side and solder quickly with high heat.

EDIT: Strange that the other drawings on the TI datasheet do not show a belly pad on the IC or in the recommended footprints. I suppose that your layout diagram helps to cool somewhat anyway, but not as well as it would with a belly pad.

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Good to know. Well I was planning on using PCBWay. On their capabilities page it didn’t really say anything about the heat so I’ll ask them directly. Sometimes the communication can be challenging. Yeah this board is not going to be high current, its basically to power a microcontroller and a couple of led drivers.

I was also looking at the datasheet for an evaluation board using this chip. They seem to implement it similar to the diagram above.

Thanks for your insights. When I started this project I didn’t really understand everything that needs to be considered to turn on a light.

To me, the TI layout looks more like improving the grounding. There is only one IC pin connected to the plane. Not a great thermal pathway.
Like Bobz, I’ve used a large via under an IC belly pad for hand soldering to ensure a good connection.

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That makes sense I didn’t even think that it would all be going through that tiny pad. Maybe if that’s the case and there isn’t even a thermal pad heat might not be a huge issue.

There is a big difference between hand soldering yourself and having others do the soldering.

When hand soldering yourself, it can be difficult to heat a pin enough for soldering if it is solidly connected to a copper plane, and as BobZ already mentioned, using thermal reliefs defeats the purpose of using a plane as a heatsink. Are you sure you want to be hand soldering this 1.7mm by 1.7mm device with 6 connections?

But you can turn it around. If you have a copper pour as a heatsink, then expose some of the copper by removing some solder mask. This way you can heat the copper plane directly with a big fat soldering iron, and heat the pad and the pin this way. Always use a bit of solder for this to make good thermal contact between your soldering iron and the copper.

Also spend some time on reading, understanding and implementing all the layout guidelines (Copy from the datasheet):

11 Layout
11.1 Layout Guidelines

  1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation.
  2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize trace impedance.
  3. Provide sufficient vias for the input capacitor and output capacitor.
  4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
  5. Do not allow switching current to flow under the device.
  6. A separate VOUT path should be connected to the upper feedback resistor.
  7. Make a Kelvin connection to the GND pin for the feedback path.
  8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has ground shield.
  9. The trace of the FB node should be as small as possible to avoid noise coupling.
  10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize it’s trace impedance.

Different traces (“tracks” in KiCad speak) are made a certain way for specific reasons. It is certainly not a good idea to use copper pours for each pin. The track for the feedback pin for example should be both short and narrow to pick up less noise, and have less capacitance to the GND plane below. Also try to keep it away from other tracks

And what are these two via’s doing?
The left one may be partially in a GND track, but the left one may even cause a DRC error with the feedback net.
Showing the zones as solid instead of outline would have been much clearer in the screenshot.

The surface mounted stuff will most likely be reflowed by your manufacturer rather than hand soldered. This avoids the problem of transferring enough heat to the board with solid connections. There are, however, other issues to consider - trying to keep zones of similar thermal capacities to avoid tombstoning small components, for instance.
If you are hand soldering, you can make things easier for yourself by putting the board on a hotplate.

Would using the adhesive layer help for this? I’m primarily familiar with it’s use for keeping SMT components on the board during wave soldering. (Otherwise one has to pick their SMT parts out of the wave solder machine’s solder pool…) But (if the assembly house supports adhesive layers), couldn’t it also be used to mitigate/prevent tombstoning in problematic areas? Or would this be like when the Mythbusters used a chain gun to shoot fish in a barrel?

Yeah I was planning on getting PCBWay to assemble this board, I have a hard time soldering through hole components let alone something in this small a package.

I was reading those guidelines and actually had an initial layout using these. Someone on reddit mentioned I should just use the evaluation module design instead since its proven. In that case they do have power planes coming out of every pin. It does seem like a direct conflict with point #8.

Thanks for pointing out those vias. I had a few more that were out of place too. I was debating the best way to display the zones, good to know filled is probably better for viewing.

All these icons on the left side of Pcbnew are for changing the way how stuff is presented on the monitor:
And they are specially there for quick access to match what works best for what you’re currently doing.

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