Pad too close to Pad message from DRC for SOIC footprint taken from official library

Hello all,

I have a board where I use said footprint. I originally had 2 ICs using this foorprint. Then I copied those two in the schematic editor, but the exact same footprint not gave a bunch of errors in the copied version of the footprints.

I think that the footprint has changed so that the clearances between pads overlap and I get errors.
See the screen shot below

Check so you don’t have two copies on top of each other.

I checked. I changed all the footprints and after that they all give ERC errors like shown.
I think it came after an update about a month ago.

Perhaps someone can check if the issues persists on other machines than mine :slight_smile:

Change the Pad clearance in the Footprint Properties.

I think it’s the pad that is too wide. It’s 0.5 mm, but according to this document, the max measurement is 0.38 mm

I made a new version with 0.4mm pad width and that works fine.
Maybe the footprint was changed and not properly checked. It made it hard to solder without solder bridges.
Can we have the footprint changed so that others don’t have the same issue? If it is confirmed to not only be an issue on my computer, of course.

No, that datasheet gives the package measurements only. The footprint’s pads must be wider than the pins. They could be narrower than 0.5mm, though:

In its current form, it creates problems with solder bridges.

0.45 can work too without ERC errors.

Point 1: You mean DRC (design rule check). ERC (electrical rule check) makes no sense in the context of the layout.

Point 2: A lot of footprints (including the one you show) of the official lib are generated with respect to IPC-7351B. This ruleset defines the relation between package dimensions and land pattern (by defining how tolerances are respected and what fillet size to aim for). All other drawings of datasheets are ignored.

So why do you get the error? Well your net clearance is too large for the chosen footprint. If indeed this is the smallest clearance your manufacturing process can allow then yes you will need to reduce the side fillet. The official library can not be made to fulfil everyones requirements. So it is to be expected that some users will need to make their own footprints. (In this case a reduced side fillet might mean that packages at the extreme end of the given tolerance range will not be able to have the side fillet expected by IPC)

Additionally, note that IPC switches the ruleset for the side fillet at a pin pitch of 0.625mm. We have often wondered if it would be better to move the cutoff point to 0.65mm as these parts seem to result in clearances not easily manufactured with typical low volume fabs.


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