Pad-to-pad spacing error in DRC

I created a custom 64-pad QFN for a TI MCU. The DRC flags a pad clearance/spacing error for the vias in the thermal pad (Pin 65). I have these holes set as Pin 65 GND in the netlist and they are connected to GND in the schematic. No netlist errors. I have the Default Net Class clearance at 0.07mm in the Design Rules and it clearly doesn’t mind the much closer 0.5 mm pad spacings on the perimeter of the device. I searched through these forums and am out of ideas.

Seeing the actual message could help. You can also show the footprint file because it’s plain text.

Is it possible that the small via pads (the pads the errors point to) have a different pin number to the large smd pad? (From the screenshot i woud guess the large pad has no pin number assigned. Give it the same pin number as the other pads and everything should be ok)

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Here is the error message:

That solved it! Problem ist geloest…vielen dank Rene.

Good. And that can also be seen in the message: “Pad 65 on…” and “Pad on…”, the latter has no pad number.

For reference, here is what the QFN footprint looks like with the pads properly numbered:

Note that the rounded edges of the perimeter pads are separate, overlapping circular pads. They must have their own corresponding pad number to avoid a DRC error.

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