Could you please tell me which clearance parameter determines the distance between pad and filled zone on the first picture below ? In footprint all clearances are set to 0, minimal clearance in PCB constrains and also net class clearances are set to 0.25 mm, but distance from the pad to filled ground zone is something like 0.5 mm - gap is twice bigger than distance to yellow clearance ring. Well, if I set non-zero clearance in the footprint I do see that zone is filled up to this clearance ring, like on second picture, but still want to understand whatâs going on with default settings.
And second question. Is it bad or good idea to allow ground to go between pads like on third picture ?
But it not explains why, when footprint clearance was set to non 0, this zone clearance was ignored. The biggest should be used. I think.
It is good idea to allow GND to go between pads. I sometimes change pad shapes to oval to allow for it. From EMC point of view GND fill should be as continuous as possible. The bigger opening (highest dimension counts) the worse. 1mmx100mm opening has the effect like 100mm diameter circle opening.
Didnât checked it but I think that if you have small clearance for footprint than all its pads use it so if pads are close to each other they use this (smaller then global) value and it is OK. But if zone has bigger clearance (OP didnât changed zone clearance) then, even pads have smaller one, zone should not be able to go closer to them than zone clearance says. If two copper things you consider have different clearance the bigger one counts. I think.
We donât know what is the zone clearane in OPs PCB but it looks that it should not be the reason as making footprint clearance smaller would not allow zone to go closer.
Select exactly two items, in this case a pad and the zone, and use Inspect â Clearance Resolution. You may find a hint.
Each pad has Clearance Overrides tab in Properties, so does each footprint, and zones have their own clarances. Sometimes finding the culprit is tricky.
Up to now I didnât touch zone clearance and it was 0.508 mm initially. I agree with Piotr that itâs a bit strange that it is ignored when I put smaller clearance for footprint. But anyhow, now I know how all clearances work. Thanks a lot for explanation!
If you are using V8 (we donât know that, I think) than it can have relatively lot of bugs so it can be the bug.
But if you are using V7 than it should be rather free from bugs.
And concerning clearance resolution: when footprint has non-zero clearance, clearance resolution reports only this:
Clearance resolution for:
Layer B.Cu
Zone [GND] on B.Cu [netclass Default]
PTH pad 3 [] of REF** [netclass Default]
Local override on PTH pad 3 [] of REF**; clearance: 0.2500 mm.
Resolved min clearance: 0.25 mm.
And once itâs known, I would not consider this override to be a bug, I would call it âfeatureâ
Override by local settings the global settings is OK (pads now have 0.25).
But if the other copper thing (zone) has higher clearance (0.5) than concluding that Resolved clearance is 0.25 is bug.
What if you have 200V zone and because of 200V you set 2mm clearance. Than it happens to be near 0.4mm raster IC that you have set its clearance to 0.15mm. You think that going with this zone to that IC with 0.15mm clearance is feature because itâs known. I donât think so.
Do someone using V8 can confirm it and may be report a bug.
In my opinion, if it is as it looks from this thread it is a critical bug as can lead to not noticed ordering PCB not following needed isolation.
I can confirm that setting the clearance override in a pad forces that clearance between the pad and a zone of another net. But this happens in v7, too.
On the other hand Piotrâs reasoning is clear. But one use case for pad clearance is a small pitch component where the pins are closer to each other than what the design rules otherwise allow. It would be difficult to use custom rules etc. to allow connections there without this feature. It may be intentional. Clearance overrides in footprints and pads should be used sparingly.
I understand. If you want to work with 0.25 clearance everywhere but near small pitch component (I use components with 0.18 mm distance between pads) you accept smaller clearance than it is feature. And may be such decision was made.
Now I think that may be reasonable assumption should be that local clearance can override only global settings. If two local settings meet each other may be the bigger clearance should win. I donât know (never checked, and donât remember to read about it) if zone can have clearance 0 meaning - use global for this net. I assume that zone clearance setting is âlocal overriding globalâ and being higher then met the second local one should win.
I used to set higher clearance for zones than for standard tracks as zone is in paralel to other tracks at long distances. In past (90s) it resulted with higher probability of shorts so I just used to have it bigger (0.25 compared with 0.2 my standard).
I would be surprised if suddenly zone will be closer to something. For any other things I can manually shift them but zone (placed at whole PCB) in aspect of clearance is out of my control. You have a control by setting its clearance but now it looks it doesnât work.
I suppose in clearance selection in past (should check in V5) it was the rule âbigger winsâ, while now it looks it is âsmaller winsâ. May be it should be spend some more time on finding the best, probably complicated, way of solving this issue. May be developers spend on it days and simply there is no âthe only right solutionâ to be used.
May be the problem of elements with small pitch should be solved by local (for area at PCB and not footprint) rule allowing all tracks (not zones) in that area to have smaller clearance to other. It will allow to make locally connections with smaller clearance.
Edit - next thought.
May be such area could be linked permanently with footprint (in footprint editor) to not have to move it whenever you move footprint. I wonder if current local setting have such effect or not. Iâm not sure.
