hi im new to this software so bare with me. i have a specific mosfet i want to use FDC640p cant find this anywhere in the listing ive looked at some of the P channel ones but nothing seems similar has anyone used this mosfet before and may have schematic symbol for it?
thanks in advance
For this FET i would make my “own” footprint based on the SOT-23-6 you can find in the standard footprint libs. There’s not much to be done other than renumbering the PADs based on there connection taken from the datasheet / your schematic symbol. So for example if you choose the symbol Q_PMOS_DGS you could number all PADs connected to the Drain 1, the Gate 2 and all connected to the Source 3.
So you really can choose whatever PMOS symbol you like as long as you then number the PADs on your footprint the same way.
I advice against making a specialized footprint of a standardized package as this will make your footprint lib impossible to maintain (Just think about the day when IPC-7351C replaces IPC-7351B, you now need to replace all your footprints to stay compliant.)
My suggestion therefore is to have a library of generic footprints with standardized pin numbering and make a fully specified symbol for this part that either uses stacked pins for the package leads that are used for the same “signal” or possibly even have every one visible. (Depending on your preference)
Depending on what you do there also can be restrictions on how your symbols have to be drawn. So it may be necessary to do what i wrote. In this case it is also very likely that IPC-7351 is not a thing.
Apart from that, you are much more knowledgeable than me when it comes on how to handle KiCAD Footprints or Symbols. So a beginner should rather follow your advice than mine.
Unless you plan to stop working in electronics within a few years you will experience changes to PCB manufacturing processes which will likely require your footprints to be adapted (The reason why IPC rules change is not because somebody thinks it is funny but because manufacturing techniques evolve). Nothing similar to that can happen to symbols (while you will likely want to adapt the additional information a single fully specified symbol holds as time goes on it is highly unlikely that you will need to do any global adaptations to them.)
To be honest i have yet to be given any convincing argument for specializing the footprints instead of symbols. All arguments i got so far where along the lines of having the option of using the footprint exchange tool to select which component is used near the end of the design process. But here i argue exchanging fully specified symbols is not really more work than manually entering the BOM information as required by the “flexible” workflow.
This of course assumes that all exchangeable symbols are designed such that they can be easily dropped into the same place (So another argument for stacking pins instead of showing every available pin)
The answer to Vindi’s question is that in schematic you use the existing lib Symbol for P mosfet. The symbol is generic.
In the schematic editor, with the cursor on the Fet, use ‘V’ command to enter the specific part number.
I suggest you watch some introductory videos to pick up the basic methods.
Please all keep in mind vindi93 is requesting a schematic symbol. Given the 6 pin SOT package, the symbol needs to have the correct drain pin connections to correspond to 4 drain pins in the footprint. PCh MOSFETs in SOT-6 are not the most common but not so rare either so something probably exists. I think I have built boards using Pch SOT-6; before I got with KiCad. But I like to edit my own schematic symbols anyway.
Rene; the original question concerns symbols; is your point relevant? (I am not familiar with the standards at all).
BTW for SOT-6 MOSFET Footprint (not schematic symbol) I like to put the four drain pins on one big fat pad. This is good thermally and performance-wise. My resulting footprint looks like an oversized 3 pin SOT. If you want to do that then you might want to define the symbol as having only 3 pins. These are methods I use for my home-built boards; perhaps some manufacturing operations would object to doing things this way. But it is easy to hand solder and works well when powered up.
I did not directly answer the original question but corrected (or made a counter argument) to @Detzi.
This FET is for low power so i doubt it needs the extra thermal contactivity of solidly connected pads. To be honest such a pad would make it very hard to solder so i would really suggest using a copper zone with thermals instead of using a large single pad. And even if one wants to make the tradeoff in the direction of thermal contactivity instead of solderability then i would still use a copper zone but this time with connection set to solid.
There is no generic symbol for a 6 pad footprint, so @vindi93 will need a specialized symbol or make a specialized footprint. I highly suggest going the specialized symbol route.
Thanks again, Rene
I view the situation differently. The SOT-6 is designed for higher power (and better dissipation) than a SOT-3. MOSFETs almost always run better when cooler, so I want to provide more cooling copper rather than less. Sometimes we want a smaller MOSFET for a variety of reasons, including reduced gate charge or perhaps price. In many cases, the MOSFET ON resistance is used as a sense element for current limiting. Or maybe those are the parts we are using elsewhere. So cooling a smaller MOSFET with added copper zone may well be more attractive than using a larger one without extra copper. I almost always avoid thermal relief in this situation as it largely defeats the purpose of cooling the FET.
After my post I thought about it and realized that a top layer copper zone is probably the best way to go to cool the FET when using competent tools such as KiCad. It avoids confusion when you have the schematic and footprint agree with the device datasheet. Using one big pad invites confusion if the device obviously has 4 pins. I had previously done many boards with ExpressPCB which has no DRC, and the cheapest boards have no solder mask. So you mostly do whatever you want and be careful as heck to avoid stupid errors.
One more thought: When I was an apps engineer at a semiconductor company, our power eval boards would often use a footprint which could accommodate a variety of packages so that the user could experiment.
This example shows how a SOT-6, SOT-23, D-pak, or SMB diode could all be placed on the same pcb footprint. The schematic would probably indicate a generic symbol without attempting to show multiple drain pins. Just now I stretched the drain pad to fit the D-pak but I think you can imagine how all 4 devices would fit the same set of pads. In this case the FET may be used as a synchronous rectifier so a schottky diode in SMB package is one of the options for test.
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