@baldengineer I can get an “almost-overlap” by setting clearance override to zero or netclass clearance to zero, but it’ll still fillet on the corners and force a five micron gap:
In KiCad V7 the simplest way to go is probably still to use a net tie.
Here I placed a simple (default) net tie between two planes (thermal reliefs can be disabled easily, but I left them to show the net tie shape).
Then hover over the net tie and press [Ctrl + e] to load it in the footprint editor:
Then select the rectangle between the pad, and drag the handles a bit around:
Then just close the footprint editor. It asks you whether to discard or save your changes, make sure to save them back to the PCB:
Result:
Well, that’s inconvenient. Trial and error until you get the exact shape you need, I guess…
The board I upconverted to 7.0 has quite a few overlapping planes on quite a few layers that will all now need to be fixed. TVS diodes pointing at ‘power ground’ in the analog input region now need to change on the schematic to match whatever part of the ground plane they actually end up on. (And change again if they have to move.)
When before I could just draw a zone and be done with it.
I’ve raised an issue here: Overlapping same-priority zones no longer short-circuit as described in the manual (#14069) · Issues · KiCad / KiCad Source Code / kicad · GitLab
I’m not sure but my first guess would be that the documentation will be updated without a code change.
Not necessarily.
In the example below, I did:
- Draw a kite with: PCB Editor / Place / Draw graphical Polygon.
- Copy the kite to the clipboard.
- Hover over the net tie and press [Ctrl + e].
- In the footprint editor, delete the rectangle in the net tie.
- Press [Ctrl + V] to paste the graphical polygon.
- Close the footprint editor and [Save] changes back to the PCB.
Apart from that, instead of “guessing” you can also use the measurement tools and make some notes on how big you want things, or have the PCB and Footprint editors open at the same time. (Multi monitor works great for this).
Paul, thanks for the suggestion. I got to the point of drawing the net tie and discovered I can’t put footprints on interior layers. How can I get around this to tie an interior ground plane?
Actually KiCad supports SMD pads on inner layers, but not in the level of UI when footprints are created. You can manually edit the footprint file or the board file and just change the layer of the pad and the non-pad copper shape. (Remember to remove the mask and paste layers from the pads.)
(fp_rect (start -1 -5.75) (end 1 7.75)
(stroke (width 0.2) (type solid)) (fill solid) (layer "In1.Cu") (tstamp 2b0cf023-cd8f-4153-a15b-d75eaa108009))
(pad "4" smd roundrect (at -0.18 7.58) (size 2.286 1.524) (layers "In1.Cu") (roundrect_rratio 0.25)
(thermal_bridge_angle 45) (tstamp a4d99cc6-ee1e-4cf3-944e-6062ff8be303))
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Via?
How would you like to place footprints on the inner layers? And how would it be manufactured?
I just told.
SMD footprint pads are just copper. I think board manufacturers can put copper on inner layers. 
It would be more difficult to assemble components there…
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It’s a net tie. It’s just copper. But KiCad 7 is making this process inordinately hard as compared to KiCad 5 in which you could just overlap two zones.
I think that net-tie could be special filled area with check-boxes for each of layers you have.
I don’t know if filled polygon (with no net attached) placed at copper layer will overlap with zones or not.
I don’t know if filled polygon (with no net attached) placed at copper layer will overlap with zones or not.
The zone pour will also maintain clearance with a copper polygon.
So the only solution is to do it as a last design step (after DRC) and avoid zone pour afer it
Fixing the net ties properly is … taking quite some time. #2265 I linked to earlier has been open for 4 years, has 21 upvotes and apparently needs some more of those…
Note that while 2265 is not fully solved, net-ties were quite substantially improved in v7. You no longer need the “net tie” keyword, and you can explicitly specify pairs of pads that are intended to be shorted. For example, in a 4-pin kelvin resistor, you could say that pin 1 and 2 are shorted, pins 3 and 4 are shorted, but pins 1/2 are not shorted to pins 3/4.
The only thing from 2265 that hasn’t been implemented is single-pad net ties, because KiCad’s architecture is still one pad == one net. Single-pad net ties would let you say “pad 1 should be shorted to nets x, y, and z”. But you can get pretty close with what you can do in v7.
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As I mentioned in another comment, this is accurate for v6 but not for v7. You don’t need the net tie keyword in v7. Instead you explicitly specify shorted pads in the “clearance overrides and settings” tab.
I hope @craftyjon doesn’t mind me summarizing the changes he made here…
As of today, Jon changed the 7.0 and 7.99 branches so you can short overlapping copper zones by adding a custom DRC rule that specifies a negative clearance for the zones in question (in most DRC rules, a negative clearance means to disable the clearance constraint).
This allows OP to accomplish their goal of net-tie-with-zones.
Jon’s example DRC rule is:
(rule net_tie_zones
(condition "A.Type == 'Zone' && B.Type == 'Zone' && A.NetName == 'GNDA' && B.NetName == 'GNDD'")
(constraint clearance (min -1mm)))
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That’s great news – thanks for sharing it! Since it’s in 7.0 will it be built into an official release? Will I need to do anything specific to get this functionality?
just update to 7.0.1 when it’s released, or use tomorrow’s 7.0 testing build.
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Sounds good.
When I have written:
I was thinking about making at inner layer GND_A island inside GND (rest of that layer) and connecting them by added filled area. Now with adding GND_B net and two negative clearance rules I suppose it will be possible with GND_A being automatically isolated anywhere else from GND.
Oops. I see a potential problem. Will GND_B fill be not removed because of lack of pad it is connected to?
The footprint with pad at inner layer will be needed.
No, fills with zero pad connections won’t be removed as islands.