Overlapped optional components. How?

Layout Footprints
#1

I want to create a board with two variants of IC: SO8 and DFN8. When I place two footprints one inside other I got DRC error. If I create own footprint with two sets of pads I can’t control solder paste apply.

Is there any way to create two-sets-of-pads footprint with solder paste control (I don’t want solder paste under SO-8 IC, but it is ok if it applied around DFN8) ?

#2

I am all in favor of layouts which accept varied semiconductor footprints. I think I have made footprints with two pin 1. two pin 2, etc. Did you try that?

Another possibility may be to make weird shaped pads which include the pad for both footprints.

Most of what I have done like this is for hand soldering…no concern for solder paste (or for toothpaste either.)

#3

Assuming KiCad knows (from schematic) that they should be connected one to one I suppose may be there is not enough space between SO8 pads for DFN8 (didn’t looked to it) and clearance is violated.

I would try to delete one of them before generating paste gerber.

#4

There’s certainly no explicit support for this, and I can’t see any semi-automatic way, either. The paste layer would need support for support for alternative layouts, and that would be much larger and complicated feature than just adjusting the paste layer.

BOM is another thing: to automate it you might need assembly variants. That’s also a complex feature, a feature wish tracked in Create a PCB assembly variant system (lp:#1767218) (#2131) · Issues · KiCad / KiCad Source Code / kicad · GitLab. There’s also some discussion about layout variants there.

#5

The PCB can be made with two different footprints for a single IC, but you would indeed have to make two different solder stencils.

I am also not aware of direct support for this, and the easiest method is probably what Piotr already mentioned:

  1. Save your project.
  2. Delete the footprints you do not want from the PCB.
  3. Generate the Gerber file for the solder stencil.
  4. Exit the PCB Editor without saving.
  5. Restart the PCB editor.

I recommend to exit the PCB Editor just after the Gerber for the stencil is created, to prevent the PCB with the deleted footprint from getting saved accidentally.

#6

I’m looking for a way to make this using gitlab ci, Kibot, Kiauto. I’ll check if I can delete footprints using CI tools.

#7

You don’t say what DRC error.

  • It is just a courtyard conflict? If so, in this very specific case you can ignore that error.
  • If it is a copper-to-copper clearance issue, what is your defined clearance based on? If it is based on your manufacturer’s absolute minimums the overlapped footprints may not be manufacturable. If your clearances are based on your own personal best practices, check to see if the clearance issues disappear when you change to the manufacturer’s absolute minimums.
#8

Yes. It is just a courtyard conflict, but i’m using gitlab CI tests and fabrication and don’t know how to ignore specific errors. I think there is a way to make footprint without coutryyard.

#9

I confirm to have exactly the same annoyance, (in my case) it shows as “Courtyard overlap”

What I do is add the errors to Exclusions in the DRC dialog.

I have some boards where not just a single component has two footprints, but to optimize space I have multiple components on the same courtyard of a single larger one.
An example is a DIP switch, that when not mounted is substituted by a set of small 0R resistors, right in the area where the switch would be otherwise assembled.

#10

I confirm that automating the BOM generation is itself an issue to consider. Given the alternative, of maintaining two different designs, I find it more acceptable to rework manually the BOM… :person_shrugging:
That is: this is true in my very personal case, with relatively small and simple boards :smiley_cat:

#11

I see two possibilities of resolving specific courtyard problems.

One way is to ignore specific courtyard violations. You can right click on any violation in the DRC window, and then click on Exclude this Violation in the popup menu:

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Another way is to edit a footprint and then simply delete the courtyard from it. To do this, just hover over footprint in the PCB and then:

  1. Press [Ctrl + e] to load it in the footprint editor.
  2. Remove the lines from the courtyard layer.
  3. Close the footprint editor.
  4. KiCad asks you if it should save the changes in the PCB, confirm this by clicking on Save.

If you want to do this for multiple footprints, then also:

  1. Save your modified footprint in a project specific library.
  2. Update the schematic to use the footprint links to that new library for every footprint you want to change.
  3. Schematic Editor / Tools / Update PCB from Schematic [F8]
#12

@Alexandr_Shutko you can tell KiBot to ignore specific DRCs with a preflight filter. You should be able to use that to exclude the courtyard overlap violation. For example, here’s a filter I use to ignore an edge clearance violation in one of my designs with a castellated mounting hole.

preflight:
  filters:
    - filter: Ignore board edge clearance violation for castellated hole on J1
      error: copper_edge_clearance
      regex: (?s)Edge.Cuts(.*)J1
1 Like
#13

@cdwilson thanks! I did this allready - it helps. There is one problem left - solder paste on inner footprint when I don’t want to place it. Looking for a way to generate paste gerber layer without inner footprint.