Overlaid Footprints

I have a situation where I can use either of two ICs in a particular circuit location. Both are SMT but one is appreciably larger than the other. Smaller one can actually be nested inside the larger one (think SMT logic inside a through-hole footprint of the “same” device) I get DRC errors if I just place the small one inside the larger one. Of course, I could just live with the error. Motivation? This is a fairly tight layout and having the footprints spread laterally also means bypass caps for both, adding to the occupied board area and BOM complexity.

Being one who tries to avoid even warnings, I wonder what alternatives there might be. I guess I could create a new hybrid footprint with both pad patterns in the single footprint. But, that sounds like work, and work is another thing I try to avoid :=)

Any suggestions would be appreciated

Jim Wagner
Oregon Research Electronics

What are the errors exactly?

I do that all the time.
It works with a simple user-defined rule.
Which version of Kicad are you using?
The rule is different between 7.0, 8.0 and 9.0. This is due to the ongoing development of the DRC.

Sorry to be slow to respond. I made changes and cannot easily get back to the original error message. And, I am still on 5.x because I do not want to change in the middle of a significant, multi-board, multi-year project.

I’ll just create a new double-chip footprint. Its not THAT much work.

Jim

Sounds like a biggie. I have done combi footprints but mainly for transistors; not ICs.

Sorry, I can’t help you with 5.0.

Jan

There are some features that make for me V8 really preferable over V5. For example to make my PCB drawings to be used in documentation in V5 I had to export several layers into svg files and then use Inkscape to make copper gray and all them together (I don’t know why files imported to Inkscape don’t want to be just at the same positions). In V8 I get the final output file directly from KiCad in one move (select my output color palette, export, select working color palette). Generating my BOM is also simpler/faster in V8 than in V5.

In your case I would give last V8 version a one/two day try in the way allowing me to get back if my decision would be: “No, I can’t work with it.”.
When moving V5-V6-V7-V8 I have never noticed any problem. I have only had to open my previous schematic/PCB/library and accept saving as new version. But I have never did it with skipping versions. Whenever new version is released I spend a hour opening and saving all my projects (except prototype projects that I don’t expect will be doing next revision).