Opposite of a net tie?

I have just preliminary completed a 4 layer pcb design. I am looking at the price difference between a 4 layer and a 2 layer board. But the issue is…if I delete two layers, I would probably would want to use a few jumper wires to distribute my DC power without chopping up the ground plane too badly.

Here is my thinking…A net tie is a way to electrically connect two nets in a way that DRC does not recognize as an electrical connection. But a jumper wire is the opposite. It is a way to connect portions of a net using a wire as a physical component which does not appear on the schematic diagram. Ideally I would like to put in some footprints which DRC will accept as in-net connections. I am guessing there is no ideal way to do this.

Of course I could re-do the schematic and make some sort of symbol for a wire between different nets…but when I draw the schematic it is not so easy to plan that way.

The best thing I can think of is to run DRC with the third layer in place (maybe have a blank fourth layer) and then simply delete the two added gerber files. Traces in the third layers would be replaced by jumper wires which had better have PTH tie points. This might be OK but seems like a cheat which could open some risk of errors. Any better ideas?

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Or just not generate the inner gerbers… You would want to make sure of two things:

  1. The vias you use to connect to the inner layer(s) that you will eventually use as documentation for putting jumpers are large enough to accept the gauge jumper wire you plan on using, and have a large enough pad to solder to with your personal soldering skills.
  2. When generating the gerbers you select “Do not tent vias” so you aren’t scraping solder mask material off of the via pads, and potentially out of the via hole.

For signal nets, 30AWG (wirewrap wire) is probably sufficient, and will keep your vias to a small and manageable size. (I’ve modded boards using wirewrap wire plenty of time and the boards still worked when flown into the stratosphere (and all the extra radiation up there) for several days under a big balloon. So it should be fine down here under the blanket of atmosphere.)

For power nets, calculate the maximum expected current load and use a wire gauge calculator to determine the appropriate gauge.

Thanks, SembazuruCDE

The thing that I do routinely is make a “test point” (for AWG 24 or AWG 20). This has two normal through hole pads which accomodate a short piece of bare wire. I usually connect both pins to the same net. Anyway no worries about tented vias if I have one of these at both points which I want to connect.

These jumpers would all be for bias current; < 50 mA or so.

The designs we did at that job all had a 1" ground connection. Similar idea, two holes spaced about 1" apart both connected to ground. Then a piece of buss wire (non-insulated solid wire, I forget the gauge, but probably 20AWG) soldered across about a quarter inch above the board (kind of looked like a large staple sticking up from the board). This ground connection was used for connecting the ground lead of o-scope probes and/or DMMs when troubleshooting.

That sounds good. Of course sometimes board space is a luxury. But if the space is available then placing test points are one way in which some care before tapeout can save time and trouble during board test. The home-made wire test points are OK when lab time is cheaper than the price of purchased test points. Also some of the purchased test points require proper mechanical insertion for good soldering. The home made test points work OK when the assembly tools are a needlenose and diagonal wire cutter. Two PTH pins work much better than one.

It’s been a few years now since I last cobbled together a decent digital board with Vero board and “enameled” wire. There are no real ground planes on such a board and I used to drill 2 holes of 2 to 3mm into the boards near a big buffer cap. Each hole had a bunch of these “enameled” wires an so I had star distribution of both Vcc and GND, and of course a 100nF decoupling cap near each IC. I’ve never had problems with this setup. My most complicated board hat an ATmega uC, 2 static 32kiB rams (Cache chips salvaged from 80486) a programable logic thing from Lattice and about 10 TTL IC’s. But my boards never had to pass an EMI test.

The most trouble I’ve had was with long cables (5m UTP) hanging off a board. These pick up enough noise from for example turning on FL lamps to upset microcontrollers, an I’ve managed to get these troubles under control with ferrite cores and inductors as filters. An inductor from a small SMPS circuit keeps out a lot of noise from external cables that an LM317 does not.
These troubles may have been worse because of the lack of GND planes on my Vero board.

Laying out a 4 layer board with 2 dedicated power planes is much easier then laying out a decent 2 layer board.
The higher the frequencies are you need to fight, the more important “loop inductance” becomes, and this is where continuous GND planes become real important. Ideally you want a continuous GND plane right underneath each signal line. On a 4 layer board it’s easy (Unless really complex) on a 2 layer board it becomes a gamble on what you can get away with.

For a small batch of boards it may be a good idea to put on a bunch of jumper wires by design. For lager batches it quickly becomes tedious, and for larger batches the price difference is also smaller.

Sometimes you can make a decent 2 layer board by alternating the GND plane between the top and bottom, and stitch them with plenty of via’s.

I’m also for “cheating” with using some layers as “wire bridges”, and those layers never make it to the fab. Just use large via’s with holes big enough to poke your wires through, and as SembazuruCDE suggests, don’t tent them, check your Gerbers. It’s not cheating if it works.

I’ve got a nice photograph of a TTL board made in the early 80’s. It’s got about 100 IC’s and is routed in the classical way with horizontal tracks on one side, and vertical tracks on the other. Such routing was common back then.

See at least https://gitlab.com/kicad/code/kicad/-/issues/2558 and https://gitlab.com/kicad/code/kicad/-/issues/2068.

The question comes up regularly in one form or another.

In the need like this I have just did it that way. It was not in KiCad. There I had buttons to “Place Via” and “Place Pad”. I needed only 2 wires so I used 4 times “Place Pad” (THT pad).
And I didn’t deleted extra gerber - I just didn’t generated it.

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