I almost never use these options but you can rise a feature request. Anyway seeing the workload of developers in fixing bugs and implementing other features I think this priority will be low, very low…
The problem with open drain is that your sewage ends up spilling onto the floor.
I often use bipolar transistors. For small signal applications, I will use a bipolar if it works OK, and only go to a MOSFET if it offers a clear advantage. Saving one 0603 resistor does not count as enough of an advantage IMO.
MOSFETs are better for some things but not for everything. I can drive the base of an NPN using any reasonable voltage source through a resistor, and I do not need to worry about needing a voltage clamp zener.
Somewhat semantic. IMO there are other issues that are more important.
Sure, call it “Open drain/collector” if that’s so important. Engineers understand the function.
I am using bipolar transistors as I don’t know important advantage of CMOS. I thought that I can save resistor in base but sow a discussion where people were writing that gate resistor is pretty mandatory to limit gate capacitance loading current pulses.
One of my typical npn use is driving its base from 3V3 logic output and using it as current source to drive LED supplied by higher voltage. That way I dissipate power in transistor and resistor instead of voltage regulator that happens to be SOT23. Replacing it with NMOS would be complicated.
As OC TTL level output (with typical 4k7 to 5V pull-up) I also use npn. I form from output transistor a current source (about 16mA) so if output has 0 state and surge pulse happens to reach that output the high current (I assume 25A) will go through transil and current pulse power in transistor will be limited to about 16mA*25V (18V transil) = 0.4W.
Suggest the comparable NMOS solution.
One example of where a small signal Nch MOSFET can be helpful: If I want a high level open collector output from LM339 to close a switch to ground…let’s say I am switching 1 Ampere for a load of some sort. In that situation an NPN bipolar base will significantly load the resistor pullup LM339 output high level, but a small MOSFET will only add a bit of capacitance so slow it slightly. So the LM339 output is mostly unchanged by the connection to the MOSFET gate.
More often I would TRY to drive my load with a common emitter PNP (MMBT4403) on the high side, so the PNP would turn on when the LM339 output is low. This would be good for a 100 mA load for example but might not be what you want to do…
Internally max current I have to switch is about 20mA so I use BC847. Externally if I have to switch up to 1A I use 7A OmniFET or InteliFet (for little lower current) that are practically IC and not single MOSFETs.
Um, wasn’t the question about open drain or open collectorr outputs in symbols?
That’s relevant for ICs, not discretes, I think.
That aside, open collectors are much more common than open drain.
Give me a few more posts of Q & A, and I could steer the conversation to…um…maybe tire sizes?
Seriously, I guess that open drain versus open collector question did morph into whether we expect to continue using both FETs and Bipolars for the forseeable future. I feel safe in saying we will.
Using both makes the text string so long, which may break some window somewhere.
I have come across open emitter drivers in level shifters and the the confusingly named open source, which will get confused with opensource at first glance.
For ERC purpose, these all require a pullup/pulldown somewhere.
From a board designer’s perspective, there is no difference between open drain and open collector. Both are pull-only outputs (rather than push-pull), and that difference can be used by the ERC to recognize that it’s okay to connect multiple outputs together. Whether the ERC is that smart I’ll leave to others.
The other discussions are irrelevant to KiCad and thus off-topic.
But Open Collector/Drain would normally be used for logic chips within a family. e.g. to indicate that wired-or is ok. It would not be used on single transistors unless you think it could catch more errors than Passive. And Open Drain would not catch the rare case where you are mixing logic families of opposite polarity, e.g. it would be disaster if I thought the Open Drain of my ancient PMOS clock chip would be ok with the Open Drain output of a NMOS logic gate.
Maybe you need a prescription of anti-ercamine. Generally I usually get only pin not connected or unit not used warnings which are easily solved. The DRC consumes more time.