Hi.
I have a circuit for a device that I want to build into a 19" rack case. So the circuit will be divided into; front-panel board, rear-panel board, main board etc, and the boards will be connected with cables. I want to layout the boards in one project and separate them with V-grooves.
What would be the proper way to approach this?
I’m thinking I should do a hierarchical schematic with separate GND for each sub schematic. But I’m not entirely sure this is the best way to go about it.
I did that (professionally) many times.
My advice is : one board, one project.
For example, If you make a mistake or want to change something on only one prototype board, you certainly don’t want to relaunch a fab for all the PCBs…
You can make a panel if you want, but it may depends on the PCB manufacturer
for low volume / hobby / Maker’s project, using online PCB fab, I don’t know what is the less expensive : individual PCBs ou one panel.
For the final PCB’s I agree with pmx. At least start with separate PCB’s especially for hobby level projects.
If you want or need panels for automated production, then there are several ways to do so later. PCB manufacturers can make panels, and there are some scripts for in KiCad that can help with panelisation, but there is no real support for making panels in KiCad itself. You can’t do DRC on a panel for example because multiple footprints will have the same RefDes.
Quite some time ago I did an experiment, in which each PCB was it’s own project in KiCad, but I also added all projects in a “mother project” and then included the schematic sheets of the other projects into a hierarchy from the mother project.
This worked quite nice. You can do ERC over the whole project, and for making the PCB’s you can switch to the child-projects.
Others on this forum ave done very similar things and apparently it also works for them, but it’s not officially supported by KiCad.
Another thing worth mentioning is working with a template.
You can create a template from any KiCad project, and re-use that template for another project. This is for example useful if you have different PCB’s that all have to fit into the same 19" rack. For such a project you can make a template for the PCB outline, connector locations, mounting holes and other stuff that is shared between different projects. You can manually copy a project to another directory, but that is a bit finicky. If you rename the files you will run into some issues, and the template system should prevent that.
Hi Paul,
very interesting !
Do you remember if you had the components designators numbered from the top enclosing project (unique refs) or independently within each project ?
I the first case, back annotation is probably not possible, though.
As far as I can remember, I fist made some empty projects, then the mother project and included the others as hierarchical sheets and then did all the schematic drawing in the “mother project”, including annotation. ERC also needs a properly annotated project to work. I just tested it. Took a random project, renamed a resistor to have 2x “R7” and ran ERC, and it complains about annotation.
But I’ve posted it all in that thread I linked earlier, and also attached the whole project there, so you can open it in KiCad, and abuse it in any way you can think of, and then see what happens for yourself.
just made a few projects, along the lines of your experiment (two sub-projects an one top-level project).
I checked the content of the various files.
Looks like, in a hierarchical project, the parts annotation data is stored in the top-level sheet file. The sub-level schematics annotations are not updated during this process…
Any annotation data already present in the sub-level hierarchical sheets is ignored.
(At least, this is what I’ve understood after a few tests, so take my words with a grain of salt !)
Unless there is a script to force the sync of the sub-level schematics annotations, you can’t update and route the various PCBs.
IMHO, it won’t work out-of-the-box, and it’s better to stick to the foolproof “one PCB, one project” principle.
P.S. Also, the POWER_FLAGS, for example for GND, tend to clash when the sub projects are joined at the top-level.
