I just thought this might be interesting to the community. Last year, I had good results for my FPGA board with routing based on bitmaps and machine learning heuristics.
And now Nvidia gave a talk about how using placement bitmaps allows them to predict routing congestion with AI, meaning they can optimize component placements before they start the actual routing.
To me, that’s another indication that the future of automated routing will likely be based on images and feature matching.
This is a cool article. I just want to point out that in it, they are talking about place&route of semiconductors, not of PCBs. The problem domains have overlap but are not quite the same.
Indeed, silicon autorouting is in a way far simpler (in terms of degrees of freedom) than PCB autorouting. Even in digital ASICs, speed/area-critical parts such as SRAM cells/arrays, long combinatorial paths, etc are often hand-placed/routed. Some even go as far as doing large part of a CPU core manually (reportedly Apple did it in some of their iPhone SoCs).
T.
Maybe this work will lead to some placement assistance. The hard part of PCB layout i trying to anticipate the crowded parts of the board routing and reduce them
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