nRF52840-CKAA WLCSP-93 via in pad help

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Hello, I am designing a 4-layer pcb where I will be using the nRF52840-CKAA chip which has the WLCSP-93 BGA package. This is my first time designing such a high density chip. I am attaching the dimensions as mentioned in the datasheet. (pitch-0.35mm)

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My problem arises in the DRC, saying the pads are overlapping. How do i fix this any suggestions? I am attaching my manufacturer constraints aswell. So far, I had decided to go with Aisler as my manufacturer. Their design rules are: 4 Layer 1.6mm ENIG Design Rules - Design Rules - AISLER Creative Community

I understand that I must go with the Via-in-Pad design principle, which I have not done before. I would extremely grateful if anyone could help me out with this. Thank You!!

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Pads are overlapping? Are your clearance constraints higher than the clearance between the pads? Can you show the issue in KiCad?

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As a sidenote: For via in pad with such small pads it is probably best to go with filled/plugged and capped vias. Otherwise these vias may suck your solder away creating voids between the part and pad. I don’t think Aisler has these production capabilities

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