I’ve got some NPTH hole on my board, that are in the middle of a zone. And There is no hole in the copper. What setting should I use to have a hole and some clearance between the zone and the NPTH hole. I want to avoid the copper to be accessible by the side of the hole.
In particular, I just had a production issue, where the board manufacturer has plated the NPTH hole, so now thay act as big via, short ciruiting everything -it’s a 4 layers board).
In particular, I just had a production issue, where the board manufacturer has plated the NPTH hole
Yes, some pcb manufacturers (for instance my standard used supplier) interpret “copper goes exactly to the edge/hole/contour” as sign to use plating (make a via or sideplating). To have a “real” NPTH hole there must be a gap (clearance) between copper and hole/milling contour.
OK, I think that I’ve solved it myself.
in the NPTH pad setting, in the clearance overrides tab, I can specify the NET PAD clearance, and with it I get a hole in the zone (and DRC error if a track is too close.
Also I’ve change in the board setup the hole to copper clearance which was set stupidly at 0.
That is probably what as happen.
The strange part is that I’ve already produced this board before whithout any issue. But may be is was luck depend on what the engineer decided to fix or not on my design
Do you still have the gerber file set?
Usually there are two drill files, one for NPTH and one for PTH.
KiCad does not change a NPTH to a PTH depending on setting in the board setup. If KiCad treated is as a NPTH, then it would have used a clearance on the inner layers.
I’ve checked my gerber, and my holes are in the NPTH file.
The issue is just that JLCPCB have made them plated. I’ve got a quality complain open with them, but they are on vacation, so I’ll have to wait a bit for an answer.
But I’ve discovered that I had a issue in my gerber with no clearance around the NPTH, so the copper flood fill had no hole at all where my NTPH hole are.
So when JLCPCB have plated the hole (by mistake), it has created a a king of big VIA between my layers (so between de + and GND).
May be JLCPCB will just say that because my copper when over the hole, it meant that I wanted the hole to be plated, even tough they were in the NPTH drill file. I think there what a mistake on each side, one on my Gerber and one on their side about the plating.
