It’s been a while since I did a 4 layer design, could I just clarify there should still be copper fill on an internal GND layer (and no fill on other layers)?
In addition the other internal layer is used for power lines but is relatively quite free. I could copper fill this one too as a second GND layer. Perhaps no point, any recommendation here?
Regards,
Andrew
Not that I have an answer but I’m sure other’s will ask questions. Can you give a general idea what the design is for? Any high speed components? Any communication lines like USB? Is it mainly a power board for something else? Any antennas? General guidelines are just that. General.
No communication lines other than MCU and none of those go through the inductor footprint. I imagine keeping it will be best as GND will act as shielding, but perhaps I’m wrong.
There is no one correct answer. As most of my work is for prototypes, I prefer to put a ground plane on an inner layer and put tracks on the outside, so that cutting is possible. Putting the plane on the top side might reduce EMI slightly by reducing the use of 0V vias.
I do not claim to be an EMI expert (I’m not), and have never designed a 4-layer PCB.
I do know that EMI is all about higher frequency stuff, and therefore about the area of the current loops. Ideally each and every track with fast flanks has an un interupted GND (or Vcc) plane directly under or above it. It does not seem to matter much for EMI whether the GND and Vcc planes are on the inside 2 layers, or on the outside 2 layers, but as Davidrsb notes, having the tracks on the outside makes modification easier. Planes on the outside also have many more interruptions (for smd pads) than the inner layers.
For an EMI point of view there is not much difference between a GND plane or a Vcc plane. EMI deals with “high” frequency only, and all decoupling capactiors are shorts at those frequencies! It seems that often both inner layers are used for a GND and a Vcc plane. This “distributed capacitance” is a further reduction in EMI radiance and susceptability.
Have a look on the Olimexino 64 on “Made with KiCad”. It has lots of GND and power planes divided over… everywhere it fits.
Apart from EMI reasons there are also other conserns. Some manufacturers use the same (default 35um) copper thickness for all layers, while some use thinner copper for the inner layers. During production, the amount of copper on adjacent layers should also be balanced to prevent warping.
The usual method of making a 4-layer PCB is to first make the inner layers, and then add “prepreg” and copper for the outer layers. I’m not sure, but it seems that some manufacturers use a different process, they seem to make 2 thin PCB’s first, and then combine them with a layer of prepreg in between. For more money you may be able to specifiy a “layer stack” and have a custom way in which the layers are combined into a multi-layer PCB (Withing production capabilities). This “layer stack” influences what can be made with micro vias and blind via’s.
Antenna’s usually must be on a single layer part of PCB’s, but for the rest, having both a continuous GND and a coninuous Vcc plane on 2 separate layers is the optimum goal, but in practice there will at least be via holes through the planes.
When there is no other option and tracks have to be layed through the power planes, the interruptions should be kept as short as possible, or better said: Treat those planes in such a way that each return current of a track can follow the exact same route through a power plane. (minimize loop induction).
Whole books have been written about EMI design of PCB’s, and recently a 6-part pdf was posted on this forum about this topic.
The title of this thread mentions “Inductor”, but nether “inductor” nor “inductance” receive much attention in the following comments.
With some commercial inductors it is important to keep an area of the board immediately beneath the inductor clear of traces as well as filled zones. Sometimes the component’s Data Sheet will include a sketch of the keep-out zone; in other cases you can accurately predict the keep-out zone based on the inductor’s construction and dimensions (and perhaps a vendor Application Note). Likewise, the keep-out zone may be already built into a manufacturer-supplied footprint, or it may be up to the designer to add the keep-out zone when you place the footprint.
Traces in this area will be magnetically coupled to the inductor, creating a two-way coupling between signals in the trce(s), and the current in the inductor. A filled zone covering this area appears as a shorted turn on the inductor, increasing losses and lowering the Q-factor of the inductance. These effects are even present, athough to a lesser extent, with so-called “shielded” inductors because there is always some leakage flux from even the best shielded inductor design.
Dale
Thanks for the advice, it is specific to an inductor as Dale mentioned.
That’s why I posted this layout.
On there is just that namely a high frequency 1.6 MHz dc/dc converter with the appropriate inductor. Bottom area mid/left.
As recommended by the chip manufacturer the switching section should be layed out with wide, or filled copper traces for best performance. It works excellently as avertised.
But the first post seems to ask different, more general, questions. 
I was also misled by this. “Inductor” is only in the title and not in the original post.
Also added the layout of a small SMPS I did (MP1584 1.5MHz)
The copper zones of the SMPS circuit and the rest of the PCB are also far apart (around 50mm, not shown) and the tracks between those areas have some filtering. I thik I may have exagerated a bit here.
The SMPS chip is U301 (Mirrored, on bottom of PCB).
The inductor is the big circle in the lower right corner.
You will most likely experience troubles with the way you have it layed out right now.
Please refer
https://www.monolithicpower.com/pub/media/document/MP1584_r1.0.pdf
On page 16 is a clear layout guide to go by.
Do you see anything in particular?
I tried pretty hard to make an optimum layout, am aware of the guidelines in the datasheet and implemented them all.
The screenshot above may be misleading. I have 2 “unused” connectors Z1 and Z2 which are only to make it easier to make modifications if needed.
I also have a big GND plane on the red TOP layer, which can hardly be seen in the screenshot from 2019-04-18.
One of the reason I used another layout is because I have much bigger SMD components I use 1206 ( I have about 50.000 of them) while the datasheet suggests 0603 or smaller. GND planes for cooling are no issure for my design, because this design is never expected to deliver more than about 50mA in this application.
Below a screenshot of the top side of the board. the big red square is also GND.
This is the suggested layout from the datasheet:
I think the capacitance of this track with the GND plane couples noise into the GND plane, which is why I kept this area small. Could it be that the capacitance through the PCB to GND slows the switching a bit and filters the flanks of the switching?
I designed this board 2 years ago, and still have not manufactured it. Just recently I took this project out of the mothballs and am now reviewing my own board to have it send to a PCB manufacturer within a month or so (I need 5 of these boards, and it’s part of a multi PCB design. I’d appreaciate some feedback aobut specic mistakes I may have made on this board, and attached it to this post.
If anyone wants to comment, then I think it’s best to start with a PM, and then I’ll start a separate thread to split it off from this one.
2019-04-20_DCX2496_digitaal.zip (787.7 KB)
I think that is for thermal and current considerations. The part is capable of 3 amps so you potentially have a lot of current and heat in a small contact area. Your copper thickness may come into play here?
PS. I should add, if you don’t understand the manufactures recommendation it is probably a good indication you shouldn’t ignore it. This is definitely a field that the more you know the more you know what you don’t know.
The track SW under L1 is necessary for the switching currents between L1 and D1 to GND. That’s where the action is on that side of the coil. Don’t underestimate the current and flux changes involved in high frequency switching. Then we have eddy currents to consider. In some cases thermal considerations are important as well.
I had a look at the design. I most definitely would change the layout as recommended.
I’ve attached a section of my most recent high frequency (1.6 MHz, allows for very small coils) design as an example. Works as advertised. Can deliver half an amp easily. It’s designed to deliver 5V from a lousy 0.9 to 1.6V battery. C102 is a 0603 which gives some idea of the scale.
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