Nightly will not drag trace nor component if it has previously been moved around a number of times

Issue:
Trying to drag a trace segment:

  • select segment (see 1st screen shot)
  • while hovering press “d” the trace and in this example the adjoining trace disappears. See 2nd screenshot.

If I continue to hold down the “d” the cursor starts flashing.
I can drag other traces in this general area.
If it delete and re add this trace it acts normal.

I’ve seen this a behavior a couple of times.
It seems to occur after moving the group in this case, several times and likely rotating it a few times. I’ve seen it in the earlier nightlys as well.

This is a hobby project so I’m playing with grossly different layouts trying to see how clean I can get it. This causes me to move different chunks of parts “all over the place”


Application: KiCad PCB Editor

Version: (5.99.0-10116-g329577cc5c), release build

Libraries:
	wxWidgets 3.1.4
	libcurl/7.74.0-DEV Schannel zlib/1.2.11

Platform: Windows 10 (build 19041), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info:
	Date: Apr  3 2021 12:09:23
	wxWidgets: 3.1.4 (wchar_t,STL containers)
	Boost: 1.75.0
	OCC: 7.5.0
	Curl: 7.74.0-DEV
	ngspice: 34
	Compiler: Visual C++ 1928 without C++ ABI

Build settings:
	KICAD_SCRIPTING=ON
	KICAD_SCRIPTING_MODULES=ON
	KICAD_SCRIPTING_PYTHON3=ON
	KICAD_SCRIPTING_WXPYTHON=ON
	KICAD_SCRIPTING_WXPYTHON_PHOENIX=ON
	KICAD_SCRIPTING_ACTION_MENU=ON
	KICAD_USE_OCC=ON
	KICAD_SPICE=ON

The highlighted track segment from the first screenshot overlaps with the pad clearance from another net and therefore causes a DRC violation.

KiCad has never been very good at handling this. and the simplest workaround is to delete it and draw some new tracks.

Also, if you want to go for a “clean” look.
Straight rows of components look good (but are electrically completely irellevant). I would put all resistors vertical. That gets the 3V3 pads of the resistors in the middle very close to the 3V3 pads of the resistors on the outside.

Making neat rows is easiest on a relatively coarse grid. But beware where you grab footprints while moving. You can grab them by their center, or you can grab them by the center of a pad, and if you mix those, they will not line up on the grid.

Your 0.1" headers (I presume they are that) are not aligned on a 0.1" grid. I’ve made a habit of always aligning such connectors on 0.1" because of compatibility with Matrix board, and such a coarse grid makes alignment easy.

Thank you, I didn’t realize a DRC violation would inhibit the drag function.

Making neat rows is easiest on a relatively coarse grid. But beware where you grab footprints while moving. You can grab them by their center, or you can grab them by the center of a pad, and if you mix those, they will not line up on the grid.

Thank you, I was not aware (or didn’t notice) the location one “picked” the footprint could effect the grid alignment. I thought the alignment of a footprint was a function of where the footprint designer chose to put 0,0

The below is only interesting if you are curious and some time to kill :slight_smile:

I appreciate the layout tips. My definition of “clean” is likely different from yours. I’ve been designing analog/switching/logic circuits for many years for both aerospace and automotive. Both applications must meet some pretty stringent EMC capabilities. As the engineer our PCB layout would be performed by a design service so I had to relay the “sensitivity” of the circuitry to the designer. They were pretty good designers and our designs always met EMC without expensive feed through filters. We used careful layout and strategically placed capacitors and/or ferrite “beads”. I always felt I could do better if I was manipulating the layout directly.

So now is my chance to see if I could do better being the circuit designer and PCB designer. As you can see, being retired I have time to use. And it keeps me out of the bars :slight_smile:
John

And out from behind bars. :crazy_face:

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