I have enabled “Free angle mode” in the interactive router settings and unchecked the “Limit tracks to 45 degrees”, but the router keeps insisting on angling my tracks.
In general I wouldn’t mind, but I’m trying to route a QFN48 with 7,87 mill track size and the track refuses to even leave the pad when my QFN is angled at 20 degrees:
Tracks can exit the pad when there are no neighboring pads, though (see SCK_S pad 24 below):
When the IC is at 90 degrees, there’s no problem drawing the track out. Even more weird, if I add another QFN/footprint outside my main circuit and draw tracks “freely”, without underlying ratnests, it kinda works:
Any hints on how can I tell kicad to just “break out” a track from a pad without angling at the very beginning when the IC is angled at i.e 20 degrees? In other words, have a track drawn at 20 degrees right after the pad, in parallel with all the other pads.
I cannot go finer track size since my fab will most likely refuse to fabricate it (less than 7 mills, there are no guarantees).
Just a guess but clearances and ‘snap to center of pad’ might be an issue here. I don’t remember where I saw the settings for snapping to pads. It might have been called ‘magnetic’? You may want to be using the edge of the pads and not the center for better control.
Thanks for the hints @hermit! I did as you suggested, disabling magnetic pads/tracks and not aiming at the center of the pad:
But still the problem with that approach is that DRC will inevitably fail since the ratsnest indicates that the track and pad are not connecting :-/
So in other words, drawing the track from outside towards the pad, results in the image above. On the other hand, trying to draw a track from, say, NSS_S pad 34, doesn’t even show a beginning of a track
The red outlines are probably clearance tolerances. Set the grid as fine as you can, turn the magnetic snapping back on and come straight out until you clear the tolerance envelope of the adjacent pads in the direction you are going and then click to start a new segment. Maybe you can go anywhere you want after that. I just noticed the part is offset from the grid. Finest grid spacing may help.
It looks like there is little wriggle room. Is the trace width a little larger than the pad width? Just eyeballing it looks close.
I am using a quite fine grid already (0,01mm), but no dice. Tried re-enabling the magnetic snapping, for reference I’m using ESP32 footprints from @devbisme:
OK. I downloaded the footprint and tried it. All was good until I tried to rotate it. I seem to remember a setting related. I’ll take a look.
Try “Highlight Collisions” under router mode. That seems to allow me to do anything I want. I’m sure there are hot keys to switch that mode back once you clear the pad but I don’t remember them.
You may be fighting some numerical roundoff that is triggering a violation of the global DRC “Clearance” requirements. I won’t guess whether the offending calculation is in the rotation arithmetic, or the mils-to-millimeter conversion. I emphasized the major clue: because KiCAD has determined that the pad-to-pad spacing violates minimum clearance requirements, it won’t allow you to even start a trace in the region where it senses the violation.
The rounded rectangles drawn with the thin, red, lines are showing you the required clearance regions around each pad. On my display I can’t tell whether those clearance regions fall into the adjacent pad or not - it’s certainly close. (Perhaps you have an electron microscope on your desk that can help resolve the question.) Actually . . . the QFN pads are specified as 0.2mm wide, and placed on a pitch of 0.2mm. That leaves a clearance of . . . . ummm . . . 0.2mm. Or approx7.87 mils, according to my trusty Pickett sliderule. What DRC setting are you using for copper-to-copper clearance? If it’s anything greater than 7.87 mils, this QFN footprint violates clearance requirements as soon as it lands in your design. And after rounding off the rotation arithmetic, the footprint may violate even a 7.87 mil clearance rule.
I would probably finagle the clearance requirements a bit and see if it solves the problem. In the global DRC settings, reduce the clearance requirements to, say, 7.869 mils, or even 7.85 mils. Or, on the QFN footprint alone, reduce the pad-to-pad clearance requirement to 7.869 mils. Or, reduce the width of the QFN pads from 0.200mm to 0.199mm.
And if the board fabricator complains that the feature sizes are now too small, find a board fabricator that doesn’t complain. I see quite a few fabricators advertising 6 mil feature sizes as “standard production”.
