New User, First Board layout V7, Inspect Resolution tools don't fix problems

Layout
1

Good Morning, First post here, it’s a steep learning curve.
Running Linux & installed V7 via Flatpak.
Found a simple sketch of a Circuit (4 Resistors, 1 Trimmer, 1 Diode, 2 LEDs, and 9 connections off-board).

[Interfaccia PACKET per Yaesu FT8900, FT8800, FT 7800 interface i6ibe]

Drew schematic of Circuit with a few issues getting symbols, but ok.

First attempt I tried creating a protoboard for layout, but quickly realised it wasn’t suitable, so onwards to a PCB.
Laid out the footprints, seemed to go smoothly.
used traces on back Copper layer to connect pads of Footprints together.Ends of tracks snap to pads, didn’t seem to be an issue.
First beginner mistake, had forgot to add a board edge.

New Discovery! Inspection menu options.
Design Rules Checker: Managed, with a little manual adjustment of traces to get down to a handful of errors & warnings.
Discovered Nets and labelling.

Now the problems start.
Area looks too large, so manually move components closer together, and have to manually move floating traces, for a smaller board.
(Would have liked them to ‘rubber band’ as they were being moved, but that’s something I haven’t found how to do yet).

Lots of mismatched Nets. More relabelling.
Decided to add through-hole pads one end, and a 6-way connector the other.
Now nothing lines up, despite manual tweaking of back copper traces.DRC reports 25 violations and 2 unconnected items.

e.g

** Found 25 DRC violations **
[clearance]: Clearance violation (netclass ‘Default’ clearance 0.2500 mm; actual 0.0000 mm)
Rule: netclass ‘Default’; Severity: error
@(91.4400 mm, 113.0300 mm): Track [Net-(J1-Pin_6)] on B.Cu, length 21.0600 mm
@(113.0300 mm, 113.0300 mm): PTH pad 6 [] of REF**
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0240 mm)
Rule: board setup constraints hole; Severity: error
@(91.4400 mm, 113.0300 mm): Track [Net-(J1-Pin_6)] on B.Cu, length 21.0600 mm
@(113.0300 mm, 113.0300 mm): PTH pad 6 [] of REF**
[clearance]: Clearance violation (netclass ‘Default’ clearance 0.2500 mm; actual 0.0000 mm)
Rule: netclass ‘Default’; Severity: error
@(112.5000 mm, 102.8700 mm): Track [Earth] on B.Cu, length 45.1900 mm
@(113.0300 mm, 102.8700 mm): PTH pad 2 [] of REF**
[hole_clearance]: Hole clearance violation (board setup constraints hole clearance 0.2500 mm; actual 0.0240 mm)
Rule: board setup constraints hole; Severity: error
@(112.5000 mm, 102.8700 mm): Track [Earth] on B.Cu, length 45.1900 mm
etc,etc,

====
running Clearance resolution under Inspection
Hole clearance resolution for:

Track [Earth] on B.Cu, length 45.1900 mm [netclass Default]

PTH pad 2 [] of [netclass Default]

Checking board setup constraints hole clearance: 0.2500 mm.
Unconditional constraint applied.

Resolved clearance: 0.25 mm.

Physical hole clearance resolution for:

Layer B.Cu

Track [Earth] on B.Cu, length 45.1900 mm [netclass Default]

PTH pad 2 [] of [netclass Default]

No ‘physical_hole_clearance’ constraints defined.

So it shows 'Checking board setup constraints hole clearance: 0.2500 mm.
Unconditional constraint applied.

Resolved clearance: 0.25 mm.’

but after saving, and rerunning DRC, the error hasn’t been resolved and is still there.
Where, Please, am I going wrong? Am I misunderstanding that the Resolution tool is supposed to fix things? or has something broken?
I haven’t used KiCad for more than a few days, so this is my first exposure to such tools.
Thanks, in anticipation of a clearly understandable reply,

Paul

2

It looks/sounds as if you have issues on your schematic . . . perhaps you don’t have things connected properly, maybe some connections aren’t made and things that you think are on the same net actually are not . . . for example:

PTH pad 6 has no net [ ]

3

Am I misunderstanding that the Resolution tool is supposed to fix things?

Yes. The task of the resolution tool is to calculate the (needed) resolution between two items. And to show from which source this resolution stems.
It’s not supposed to correct a error. You have to correct the error yourself.

4

Read this:

to find how you can promote yourself to be able to attach your design. It will certainly help others to help you.

Use D-rag instead of M-ove.

5

This seems like a great idea for a Feature Request. A resolution tool for resolving issues: any and all issues. :grinning:

@PaulK ; Please understand, my comment, IN NO WAY, is aimed at you. As @Piotr writes; it is worth spending a little time reading this forum to advance yourself to Basic. You can see your progression by Left Mouse Click on your avatar, then another LMC on your avatar. This will show your summary.

@PaulK , @mf_ibfeew devotes many hours checking and processing program bugs and requests. I doubt he, or many other users (including myself), had used that interpretation of “resolution tool”. I wish I was able to see his initial reaction to your comment. Your comment was brilliant, highlighting the ambiguities of the English language! :+1: :grinning:

6

Thanks for all your help, I have tweaked some settings and positions of components, sorted out net names and labels, which has Improved things greatly.
For what it is, the Board area seems a little too large, so I’m thinking of going surface mount. :scream

I might have chosen a suitable smd replacement (BCX56) for the 2N3019, but there seems to be a mismatch with the data sheet and/or the symbol in the library, so I’ll dig deeper into the forums and see if anything similar has been noted.

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