I added vias in my design, of course… and didn’t change anything re defaults. I assumed all would meet the requirements set in DRC. But DRC said they were all errors! It said it violated the minimum annular ring size which was 0.2mm and they were instead 0.15mm. When I look at the vias, again, nothing changed by me, they were 0.6mm with a 0.3mm hole. That is - 0.15mm annular ring! I then checked the default net class values for a via and indeed it was set at 0.6/0.3. Unfortunately now with an extensive board there are LOTS of vias (and lots of these errors). Going to 0.7mm (changing the net class default to 0.7mm) to allow for 0.2mm annular rings means a good share of issues where there’s just no room. So I changed it to 0.65 and changed the annular ring to 0.174. I then moved the remainder as needed. This is more of a “FYI” (I’d ask: what did I do wrong", but having done PCB layout before I know not to change the defaults before even starting).
Assuming the defaults are correct and a match to the PCB fabricator you plan to use . . . otherwise you should change them.
If default PCB Constraints would be set to then allow to use anything you find (like very small pitch footprints) than they will be not acceptable for many PCB manufacturers.
Before starting PCB design you should go through “Board Setup”. During that you set Constraints and Pre-defined Sizes (including Vias) and Parameters for Net Classes. What you set should be compatible with each other.
I supposed that may be you can find it only in PCB Editor manual but I see it is mentioned even in Getting Started manual:
Sorry - not sure I understand. First note: one would expect the default parameters to be correct! They violate the DRC rules. The doc you reference says : “For the purposes of this guide, the defaults are fine.” As expected, it does go on to say you need to be sure they meet with your fab constraints, but as a starting point I’d think the defaults would be set at values that normal production fabs accept - and that you’d edit to go smaller/tighter if need be (which would require confirming that decision with the fab house). But again: this isn’t about whether or not it’s acceptable by a fab" … it’s about the values defaulted to cause errors.
I just created a new project, in both 8.0.6 (current stable) and in 8.99 (development version).
The default via diameter/hole size for the default netclass is 0.6mm/0.3mm as you say. However the default DRC constraints are 0.1mm minimum copper annulus, 0.5mm minimum via diameter, and 0.3mm minimum drilled hole diameter. Therefore, no DRC violation for via annulus with out of the box defaults.
I’m not sure why your minimum annulus was set to 0.2mm, but that’s not the KiCad default in version 8. Are you sure you didn’t change it…?
I’ve done PCB work before using EasyPC … and am aware of things like this. There would have been no reason for me to change it. That stated being new to this program I can’t say definitively that is the case. If it was changed it was not by intention. My post was to bring this up to the programmers just in case there is an issue. I would suspect this would have been caught long ago so more than likely user error. Thanks for the post.
I would say that 0.1mm is pretty darn small for an annular ring - only 4 thou. The one I see, saw - the 0.2, seemed what I was use to at 8 thou.
From your first post it seemed that you even not looked into these settings. So I supposed that may be it is not mentioned in Getting Started and not lot people starting read full PCB manual. I have read Getting Started in 2017 so many versions back and I don’t know what is there now. My concern was whether someone just starting out would find information about these settings in Getting Started and I found that yes. I didn’t look into the details. I just meant that there is information to set these parameters.