New ERC errors when migrating project to Kicad 6.0

I have a project that run pretty well on Kicad 5.
There are no ERC errors and the first version of PCB works as expected.
I intended to migrate to Kicad 6 for my new board revision but I have got many new ERC errors after importing while I did not change anything yet.
One of the error is “Global label not connected anywhere else in the schematic”.
My understanding is that I have several global labels linked together and that it picks randomly one of them and discards the others and then it says that one of the discarded global label in the other sheet is now alone.
Am I right in my analysis and how could I fix that?
Thanks in advance for your help

Unfortunately it’s really hard to guess what the problem is without having the schematic. Would it be possible to upload it here? If you had no ERC errors in V5 I don’t see why you should get this error in V6.

Your analysis is probably correct. In V5 the following would provide no ERC error

In V6, we correctly detect that this is nonsense and raise a warning. The fix is to remove all global labels that don’t connect multiple pins. Or you can set your schematic editor to ignore the warning at your own peril.

Thanks a lot for your replies.
I don’t have two outputs connected together so I guess this must be something else.

Here are two extracts of my schematic where I am facing this issue

In one hierarchical sheet I get “Both XXX and YYY are attached to the same items; XXX will be used in the netlist”

In another hierarchical sheet I get “Global Label not connected anywhere else in the schematic”

I don’t know how to avoid using labels in my scenario for connecting them together.
I have a matrix defined in a hierarchical sheet ‘A’ with line inputs driven in hierarchical sheet ‘B’ and buttons in a hierarchical sheet ‘C’.

You have two names for the same net. That’s never a good idea since KiCad don’t know what to call the net. If you really must connect two different nets together you can use a net tie (search in the forum about this), but in your case you should probably just merge the two names into one.


Regarding “Global Label not connected anywhere else in the schematic”, can you show the two places that you’re using this label?

Actually it’s not two but up to seven global labels that are connected together for each lines (my schematics is cropped on the picture).
Using a single signal name for all of them would clearly impact readability for other team members and would be harder to maintain. Theses signals are out of my responsibility and they have a real meaning and purpose.

Using a net tie does clear the warnings (thanks a lot for for the advice) but obviously it adds many elements to schematics and layout.
If this is the only way, I am questioning migrating to Kicad 6 for this specific project.

I understand from what you are telling me that what I was doing initially was not a proper way to use Kicad. I am wondering why it worked on Kicad 5 though.

There are a lot of new checks that were added in v6; they weren’t checked in v5. I believe this specific one is a new check.

If you don’t like them you can disable them (Schematic Setup → Electrical Rules → Violation Severity), or ignore specific instances of the violation that you’ve deemed OK, or modify your schematic to avoid them.

If this is the only way, I am questioning migrating to Kicad 6 for this specific project.

You have 3 ways to deal with these errors without changing the schematic:

  • if you know the schematic has no errors: don’t run ERC at all
  • in the erc-error-window you can set all errors to “ignore”
  • in the schematic-settings you can disable ERC-checks for this sort of error.

I can definitely live ignoring the warnings that Kicad randomly picked one of the global labels for the final net name.

What is more problematic for me, is that other parts using the discarded global labels seem to be no longer connected due to this operation. (“Global Label not connected anywhere else in the schematic” error)

Ahh, I think I see what you mean. That error makes it sound like the net in one of the sheets won’t be connected to the net in the other sheet, which would break the schematic compared to what you had in v5.

I just put together a quick test schematic and used the “highlight net” tool to check – at least in my quick check, the actual nets are still connected. The ERC message is only referring to the label.

The first image is the root sheet, the second is the subsheet. I highlighted the wire in the root sheet, which also highlighted the wire in the subsheet, which demonstrates that they’re still the same net.

You can also check this by selecting each wire and checking that the net names are the same:

So your schematic’s connectivity should be the same in v5 and v6 – can you verify?

This was my concern indeed and your answer really helped. I also learned two useful tips :slightly_smiling_face:
Yes they seem to be still connected like in version 5.0 despite the “Global Label not connected anywhere else in the schematic”.
Ignoring all this type of errors seems a source of trouble however as it can happen I forgot to wire a signal.

This is a bug (reporting the global label is not connected anywhere). We can fix it if you report the issue with a small test project.

As noted, this bug is only with the ERC, not actually with the label not being connected.

It works the same way in KiCad 6. The new ERC check is added to help prevent confusion when people may not understand how the net name makes it to the PCB when they provide more than one possible net name in the schematic.


Glad it helped. I agree with you that the “nuclear option” of disabling the warning entirely is not the best option – if you don’t want to change your schematic, which may be reasonable, you can selectively ignore specific violations by right clicking the violation in the ERC window and clicking “exclude this violation”. Your exclusion will be saved for that particular item, but the violation can still occur for other items. That might be a happy middle ground.

I agree the message is confusing (at best) – I’m glad to hear this is a bug. I’m taking the liberty of reporting it since I already have a small test schematic ready to go.

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You were too fast for me :smiley:!
The time to register to Gitlab and make a simple example and I realized you already did the job!

I am sincerely impressed by the amount of commitment of Kicad community!

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