At our robotics school we are considering the switch from PADS to KiCad, One of our first question is about the possibility to compare the work of beginners with a reference design. In their first semester the students must draw a medium complexity (6 pages) schematic “copying” a master schematic. At this stage their understanding of electronics is very basic and they do a lot of errors. They choose the wrong parts, label nets incorrectly, and forget connections. So we do a netlist comparison to show them were they diverged form the master schematic, We are not really interrested in the graphical apparence of the schematic at this stage but we want to check that C45 is really the 100 uF part and not a 100pF part (Sir, does it makes a difference? and that it is the same connectivity.
Is there a way in Kicad to generate a text file of the differences betweeen two netlists or two schematics or between a schematic and a pcb file?
We try to use open-source sofware as often as possible and PCB design is one of the last bastion of “commercial” software in our program. We are very hopefull about KiCad so we are looking at a lot of details to check that right now is the time to make the switch.
Thanks for you help!
André Gauthier
Internet et Robotique
CÉGEP de Saint-Laurent
Montréal, Canada
Netlist is parts list + parts attributes + connectivity graph.
Kicad doesn’t have any built in tools to do a diff on netlists but it’s not too hard to write a simple program to do it. Just keep in mind that you have to compare what the netlist represents and not the netlist files themselves as there are practically infinite number of different netlist files that represent the same schematic.
To be honest i am not sure you should even care that C45 is the 1µ cap. After all you want students to understand electronics not to duplicate a drawing. Meaning what you should care about is that whatever cap is connected to a given pin of another device is within the value range given in the datasheet of that device.
I am sure you can use the KiCad netlist to accomplish this task as it is the thing that was used in the past to generate the connectivity information for the layout (there is a more direct route now). BUT be aware that any automatic check can always only ever be a first indicator! A real check (and therefore the grade of students) must always be done by humans. If computers ever get good enough to do this job then we no longer need to educate students as we then no longer have a need for humans doing this stuff
Additionally be aware that there the standard lib often offers multiple symbols for the same device. So whatever you use to check the result must be able to support all alternatives. If you want to restrict the set of symbols then you must be open about the fact that this is because your test system is inadequate.
Be prepared that some students will not like being restricted in such a manner -> If a professor gave me such stupid rules i broke them out of spite. And i would argue i am now quite a decent engineer so it was good that my professors used their brain instead of letting a heartless machine make the decisions.
KiCad’s files are all text based, so you can do a lot with text comparison tools such as for example meld.
A very much different way of working is if you start with a complete project. Working schematic + PCB.
Then you can remove the schematic from the project, let your students recreate it and import the netlist into Pcbnew. (To do this correctly you have to use "Update by Reference, and maybe some other tweaks)
During import in Pcbnew it also tells you about changes, for example when a 100nF decoupling cap is swapped with a 100uF buffer cap.
These report files are also text based and can be saved, so this checking could be further automated by filtering messages through some (Python?) script.
Also, I have my doubts about putting your students through this. It’s mostly an exercise in how well they can act as repetitive copy machines with no room for creativity. It’s also a harsh reality, most of engineering word is boring and repetitive.
As far as I know KiCad’s netlists and other files are not sorted in any way, which makes it more difficult to make text comparisons. Maybe “skidl” is interesting for you. It’s goal is to generate a netlist from a python program. I see it as a sort of VHDL for schematic entry. It does not seem to have a way of importing an existing netlist, but part of it may be interesting to modify for making your custom comparison scripts.
I’m very surprised seeing this. All schematics (with only one exception) in our firm are 1 page. The exception is made in 1993 schematic of Microcontroller education system DSM-51.
For me 6 page schematic is high and not medium complexity
For me it is low to medium complexity. But this is because i design highly hierarchical and a hierarchical sheet is a page. So page count is not really a good indicator of complexity. Component count and net count might be better options to determine how complex a system is.
I don’t think I agree with Rene and Paul here. I do see value in this exercise. According to @Andre_Gauthier are really beginners, basic understanding of electronics and first semester students. They are learning the KiCad tool, and attention to detail. From the brief description, this type of exercise seems to be where one wants to make PCBs or modify a design from a source where all you have is either print only schematics because either that is all that was provided (copying from a magazine/instructable) or the source digital files are in a format one doesn’t have access to (you get). This can also be useful in industry where one needs to update an old design that was originally designed in a tool that the company doesn’t use anymore, or from a company that your company took over. Arbitrarily changing the reference designators would be bad because then they wouldn’t match all the existing support material.
For @Andre_Gauthier, I do like @paulvdh’s suggestion for you as the instructor to already have a pcb file (need not be fully layed out) of your answer key netlist. When the student submits the schematic you can copy your master pcb file to their project folder and import the schematic to the board (matching by reference, not ID… I forget the exact language of that import setting) as your connectivity check before digging into the mess that is the student submission.
If you don’t know many of the plugins available yet, might I suggest two that might help you?
Archive Project - This plugin will make sure that all the assets used on the student’s project are copied into their project folder. This way if your students make their own symbols they will be included in their project no matter where on their computer they save their library. IMHO it would be a good thing to require your students to run this script and then zip up the entire project folder to “hand in their work” to you.
InteractiveBOM - Assuming that eventually you will have your students make PCBs (either in-house fabrication or using a low-cost professional service) and then hand-assemble the components, this plugin will be a big help during the assembly step. See the demo linked in the github readme to play around with how to use the output of this plugin. (It is a single dHTML file that can be loaded into just about any modern browser.)
One of my objectives with this question was to discover the KiCad community. I am impressed!
I was not very clear as old teachers are sometimes (some would say “quite often!”). I am pretty sure that the commonly used tools (DRC, ERC routing etc) are mostly good or very good but I was less sure about something like this netlist comparison that will not be used in most normal work flow.
I want to reassure you, those students are really beginners, that schematic is drawn in the first 3 weeks of a 3 year technical program. I sure hope that their understantding is much better at the end of these 3 years (for those who choose to work as technicians) and still better after 7 years (for those who choose to become engineers in EE (some choose the “dark side of the force” and go in software engineering:)). And they have to draw only one page of the 6 pages design (97 parts with 388 pins on the complete design (I know because I, and they, have to solder them)) and then they have 3 weeks to complete the pcb which is already routed at 84% After 3 semesters they have a good part of the knowledge necessary to choose personnal projects and after 6 semesters the faculty’s support is necessary for a very small part of their projects. And we sure dont use this “copy the leader” approach after the first semester
Thanks A LOT for you suggestions and comments, I will rapidly do more tests because I must choose a new package and gain enough expertise to be effective in the next 4 months.
Ask here whenever you think something should be easy but looks being not. Probably you just didn’t found the right way in KiCad for it yet.
I am designing PCBs since long. Last 2 years I spend on slowly moving to KiCad. I don’t think I am effective in KiCad yet, but I am moving slowly (many other tasks in meantime).
Start with 5.1.5 version or better with pre 5.1.6 (some 5.1.5 bugs fixed).
In 2…3 weeks 5.1.6 should be released (as I suppose).
and that it is the same connectivity.