I have been getting these questions from PCB fab houses when i send gerbers. I’ve used a net-tie across two nets, as it’s meant to be done (I think).
but the pcb fabs all complain that the two nets have different names and hence are “shorted”.
is there something I’m doing “wrong” with how my net-ties are made?
is there a way to indicate to the pcb fab that this is intended? or to have it come out ok in the netlist file?
schematic;
my net-tie footprint;
example from board shop;
Here’s a net tie from the KiCad library.
The “tie” is a graphic rectangle, not a pad.
I am surprised that the fab knows or cares about the difference? I do use a graphic rectangle connected between pads, as I think @eelik is illustrating. But I used only two pads. I have even done it on an internal layer. That required a bit of finagling…
Are you uploading gerbers or KiCad pcb files to the pcb fabricator?
This website indicates spelling errors for “gerbers” and “pcb”… 
hmmm, but now i’m trying to remember why i made it a pad. it was either that the pcb DRC was giving me an error or some other pcb fab didn’t like that it wasn’t a pad.
it might also be a hold-over from way back when there wasn’t a “net-tie” available in kicad.
Why would you send a netlist to a PCB fabricator? The Gerbers abd drill files should be enough.
This is a normal thing to send HOWEVER… you also typically indicate “intentional shorts”
When I say normal … It’s the IPC-D-356 netlist. Yes several fans don’t need it and you can just send Gerber’s and drill
Fabs can use the netlist to identify issues (such as this ‘short circuit’), and to build automated test fixtures for conductivity testing.
how would you do that, normally? in a note, or on a drawing layer?
Recently when I sent a PCBA job to a well-known fab whose name starts with P, I noted that their plugin, which automatically takes one to their order web page after generating the fab outputs, generated besides the gerbers, CPL, and BOM, also an IPC netlist. I guess that’s why.
Must be “Feeling Board 4 U”. 
Seriously, here is my layer 2 net tie:
Net Tie 1.5 x 1.0_internal_2.kicad_mod (845 Bytes)
Are they the ones that ask for burgers? 
KiCad Gerber files have netlist information embedded in them.
Yes,
“Intentional shorts…”
For decent fabhouses that do test and not just etch and ship, the netlist is key
Where? I’ve looked through my Gerbers and have found no netlist info in there.
Loaded a Gerber file of a front copper layer, clicked on a random pad, and then brought up this menu:
And, when i look at the Gerber file, I see this construct:
%TO.N,+15V*%
X204063600Y-85559600D03*
%TO.P,C14,2*%
You’re right, my mistake. Sorry.
Are you sure it is a complaint? I don’t think there is anything wrong, you are using the tools correctly. I think your fab is asking you to confirm which nets are intentionally shorted by net ties, because there is no structure in the IPC-356 file to tell them this. So, this is a normal part of the process and they are just checking with you.
In the Gerber X3 stanard, there are options for specifiyng constructs that may (or will?) short different nets for the purpose of short circuit testing. As an example, PCB inductors are mentioned.
I have never looked (deeply) into this myself. My first guess is that this sort of feature is not (yet) supported by KiCad. KiCad has become quite mature over the last bunch of years, but at the moment it still does not support everything.
Most vendors do not use gerber X3. They use IPC netlist files, or maybe more preferably formats like ODB++.
