I have defined a few netclasses in a pcb project. The clearance of some of them is 0.5mm. This values make it impossible for tracks that belong to those classes to connect to pins of a fine pitch footprint.
I added this custom rule:
(rule "Reduced clearance for fine-pitch escape"
(condition "((A.Width <= 0.3 mm && B.Type == 'Pad') || (B.Width <= 0.3 mm && A.Type == 'Pad'))")
(constraint clearance (min 0.2mm))
)
but it didnt work.
Then this custon rule:
(rule "Pad clearance in U2"
(constraint clearance (min 0.1mm))
(condition "A.memberOfFootprint('U2')"))
again no good.
It seems that the violation is between tracks starting from two adjacent pads and not the pads themselves as I have suspected at first.
Is there any legit way to do this?
You can use the function intersectsCourtyard('x') for this.
This problem is recurrent, and grow every day since the chips are smaller and the impedance controlled tracks grow.
Sadly, the couryard exclusion is not a solution, because the tracks leave the courtyard before that the track can complaint the requisites.
On the leak of this function on kicad i I found a partial turnaround (not good solution) Is exclude the cleareance when the another part is a pad, and when another part is a track. On this mode you can ensure the distance to the ground plane but need take carefull at hand to another tracks.
Iām not sure if this is exactly what youāre looking for, but I have these custom rules:
(version 1)
(rule "Pads have lower clearance"
(condition "A.Type == 'Pad' || B.Type == 'Pad'")
(constraint clearance(min 0.15mm))
)
(rule "annular_via"
(constraint annular_width (min 0.075mm))
(condition "A.Type == 'Via'")
)
This at least makes it possible to have tracks pretty close on the pins of the chip, while having a greater min distance elsewhere.
Edit: I think this wonāt help you. In my case it helped me with power nets and SPI nets:
Using the rule with **intersectsCourtyard()" should at least reduce the clearance for the pads themselves, so these clearances donāt overlap with adjacent pads.
Turning on PCB Editor / Preferences / Preferences / PCB Editor / Display Options / Clearance Outlines / Tracks: Show Always may also help a bit. It gives you more feedback about what KiCad is doing.
Below an example from: PCB Editor / File / Board Setup / Design Rules / Custom Rules / Syntax help (The syntax help is a light blue text in the upper right corner of the rules entry box).
(rule "BGA neckdown"
(constraint track_width (min 0.2mm) (opt 0.25mm))
(constraint clearance (min 0.05mm) (opt 0.08mm))
(condition "A.intersectsCourtyard('U3')"))
I donāt have much experience with these custom rules so Iām at the limit of what I can advise here.
Yes, but BGA has a more large distance from the ball to the couryard border.
Another thing is make a own footprint with a large courtyard. This is not a solution, but maybe help
(Ab) Using the courtyard is a convenience because itās already present in most cases, and reasonably sized. If you need more room for the fanout, then adding a (named) rule area is probably a better solution.
For QFN, LQFP, TSSOP the right solution is as Altium do: a ZZ tolerance of rules on the entire track.
For the moment we can expand the courtyard at expenses of distance of another components like capacitors.
1 Like
Thank you all for your sincere intention to help me.
I have already tried the following:
(rule āPad to Track Clearanceā
(constraint clearance (min 0.2mm))
(condition āA.Type == āPadā && B.Type == āTrackā && B.Width < 0.3mmā)
)
I also tried this a min ago:
(rule āReduced clearance for fine-pitch escapeā
(condition ā(A.Width == 0.15mm && A.Type == āTrackā &&
B.Type == āTrackā && B.Width == 0.15mm)ā)
(constraint clearance (max 0.1mm))
)
The concept is to keep this thin track of 0.15mm just to break out of the MCU, but no luck.
It seems that the clearance violation is not between pads and tracks but tracks conencted to adjacent pads.
Again thank you all and if you come up with any idea please hit me up.
Does anyone know if there are some kind of priorities of DRC? Can a custom rule override a netclass rule?
It is a known issue and unfortunately I have not found an EDA toolsuite that handles this in a legit and elegant way
