I have defined a few netclasses in a pcb project. The clearance of some of them is 0.5mm. This values make it impossible for tracks that belong to those classes to connect to pins of a fine pitch footprint.
I added this custom rule:
(rule "Reduced clearance for fine-pitch escape"
(condition "((A.Width <= 0.3 mm && B.Type == 'Pad') || (B.Width <= 0.3 mm && A.Type == 'Pad'))")
(constraint clearance (min 0.2mm))
)
It is not the best as it has a restriction but I can live with that for now.
I dont use track width smaller than 0.15mm in any netclass and save this width only for breaking-out of fine pitch packages. It is an acceptable compromise for this design.
That said I am closing this topic, but if you think of a better and more elegant solution please feel free to drop a message here.
This problem is recurrent, and grow every day since the chips are smaller and the impedance controlled tracks grow.
Sadly, the couryard exclusion is not a solution, because the tracks leave the courtyard before that the track can complaint the requisites.
On the leak of this function on kicad i I found a partial turnaround (not good solution) Is exclude the cleareance when the another part is a pad, and when another part is a track. On this mode you can ensure the distance to the ground plane but need take carefull at hand to another tracks.
Using the rule with **intersectsCourtyard()" should at least reduce the clearance for the pads themselves, so these clearances donāt overlap with adjacent pads.
Turning on PCB Editor / Preferences / Preferences / PCB Editor / Display Options / Clearance Outlines / Tracks: Show Always may also help a bit. It gives you more feedback about what KiCad is doing.
Below an example from: PCB Editor / File / Board Setup / Design Rules / Custom Rules / Syntax help (The syntax help is a light blue text in the upper right corner of the rules entry box).
Yes, but BGA has a more large distance from the ball to the couryard border.
Another thing is make a own footprint with a large courtyard. This is not a solution, but maybe help
(Ab) Using the courtyard is a convenience because itās already present in most cases, and reasonably sized. If you need more room for the fanout, then adding a (named) rule area is probably a better solution.
For QFN, LQFP, TSSOP the right solution is as Altium do: a ZZ tolerance of rules on the entire track.
For the moment we can expand the courtyard at expenses of distance of another components like capacitors.
The problem seems to be copper to copper clearance in your Board Setup > Design Rules > Constraints causing the track problem in your image. You need to halve the clearance.
Highest priority for DRC is the Copper Clearance defined in Board Setup.
Then the DRC rules, with the last one having the highest priority.
Then netclasses and other Board Setup values. (They are actually turned into rules under the hood; your custom rules are appended after them so have higher priority.)