I’m routing a BGA and there are several pins that need to be tied to VCCO and GND. A two-pin net-tie works fine in the schematic to connect and label these pins (it is nice to have names other than +3V3 and GND for these pins), but in the layout these pins will be routed with a very short trace to a single via that connects to the proper power plane. There is no room for a pair of pads.
Is there any way to do this in KiCAD 4.0.7?
I am really new to this, so I may have misunderstood something in your question. To confirm, a net tie is a component used when you want a component to connect to a flooded area only at one point?
But in this case, wouldn’t connecting the pin directly to the net rather than using a net tie work properly because the only point that it will be connected will be through the via anyway, as the flood is on a different plane from the pin, and even if it weren’t, the other pins around it would prevent the flood from connecting to the pin?
A net tie has other uses as well. It is a workaround for every case where you need fine grained control over tracks that kicad otherwise has no feature for.
In this case he wants differing clearance settings in one area of the board then everywhere else. (near the bga @dnotq needs smaller clearances as there is not enough space for the normal clearance setting of the board.)
@dnotq i would use the net ties as follows:
Draw an imaginary clearance boundary (or even draw a real rectangle on one of the user layers.) Place the net-tie at this boundary. (with the pad that connects the net with the small clearance on the inside and the other on the outside.)
But there is another limitation. Kicad does not allow pads on an inside layer. This means you can not use this workaround if you plan on having your traces on the inside.)
There should be a workaround, if it happens to work with 4.0.7 pad capabilities. I have tested this basic idea only with v5 nightlies, but it should be doable in v4.
Create a footprint with a through-hole pad which you will use as the net tie footprint and instead of a via. The pad has only the top layer. Set the dimensions which fit your case.
On the bottom layer create a non-pad copper area around the hole so that it reminds a pad ring. Maybe it can be a polygon. It should cover the hole or overlap it. In v5 it’s possible to create a graphical circle and put it on a copper layer. This non-pad copper area is the actual tie.
Create the pad number two on the bottom layer. In v5 (the latest code) it’s possible to create a graphical circle (a ring) and make it a pad. In v4 it can be done with a group of pads which all have the same pad number, positioned so that they form a ring. Make as many as you need. It must be around the non-pad copper area, overlapping it a tiny bit.
You have to set the dimensions and clearances so that there will be no DRC errors. The footprint and pads can probably have very small clearances. There are two problems. The first is that zone filling uses the through hole’s net class clearance - not the zone’s, pad’s or footprint’s clearance. Therefore the distance between the bottom outer pad’s outer edge and the hole’s edge must be larger than the net class clearance of the through hole pad’s net.
The second problem is that zone filling avoids the non-pad copper area of a footprint. There the zone’s clearance is used. So, either the zone’s clearance must be small or the bottom outer pad must be wide enough.
Now I noticed you have two planes, so at least one of them is probably an inner layer. The workaround above doesn’t work.
Why? In KiCad pads in the same net can overlap. All you need is a net tie footprint with proper dimensions. The two numbered pads can be very small, like 0.1mm. The length of the non-pad tie copper area would be about as long as the distance between the center of the BGA pad and the center of the via. The two numbered pads would be placed in the two ends of the tie. You wouldn’t use a track at all.
Ok, that gives me some ideas, I’ll try a few things and see what happens. I’m fairly new to KiCAD, and I’ve only been messing with PCBs as a hobbyist, so I have not accumulated very many tricks yet. 
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