Net tie on inner layer or possible workaround?

Hello!

I’m designing a 4 layer mixed signal board with separate AGND and DGND planes on one of the inner layers. I’m using the ADS1278 ADC from Texas Instruments. This chip has a powerpad that is designed has a heat-sink and AGND connection point. The datasheet highly recommends connecting AGND and DGND together right under the chip.

I think I could do this easily enough if the connection point was on the outer layers (using a net-tie)- but because the connection point is on an inner layer, is there an easy way I can do this?

I was thinking about cheating and modifying the footprint to assign say half of the thermal vias (and half the thermal pad itself) to AGND and the other half to DGND. This would mostly achieve what I’m looking for, except the chip itself is now the connection point rather than the GND layer. I’m worry that this might impact the performance somewhat.

Many thanks!

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