Net Tie & IPC-356

I moved over to Aisler USA for PCB manufacturing about 8 months ago. Back in July, Aisler added a free “Smart Test” service which uses a flying probe machine to test for shorts and opens between nets. The service is free. But I keep getting some interesting results from their testing.

One which is pretty consistent is it cannot handle net ties. For instance, I have a Kicad sheet with a Texas Instruments buck converter but then I run the sheet’s outputs through three different net ties – power rails. The flying probe marks these as all short circuits because its confused with two net ties being connected but they really are not. The blog on Aisler’s site says they generate IPC-356 data. If I use a net tie, is there anyway the data could be resolved to one net on an export so my tests would resolve?

Another situation I ran into was if I had a via in a pad. So, I offset these vias from the center of the pad or moved the vias off the pads where I could. This significantly reduced the testing errors from the flying probe machine. In this case, not really a Kicad issue but a design flaw.

I was using OshPark before. But about 20% of the boards had real short circuits and sometimes the ground planes were etched through in droplet spots. Also, I suspect they would throw the boards into the bag and scratch them. Often, I had scratches There are sharp edge studs from the pcbs being cut out. Maybe they had lots of volume and were rushed to deliver. You get what you pay for.

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In my experience, I have never had a manufacturer be able to deal with net ties purely with the IPC-356 data (from any tool, not just KiCad): I always have to communicate with them via email that certain nets are supposed to be shorted because they are net tied together.

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That was going to be one of my feature requests: Generation of “Intentional shorts” and then this can be provided with the release infomation.

Somewhat related but other way round is I wonder why try to take care IPC-356 compatibility in that issue if it can’t even handle net ties.

For now, I can substitute 0 Ohm resisters for the net tie and or just eliminate the net ties.

I notice that you cannot place a net tie under something like a sd card interface because it would violate the courtyards. But I could not place a 0 ohm resister in that position either – so maybe that logic prevents an incompatible situation.


would also be useful for other parts of the ERC check, to improve the use of the PWR_FLAG over both Net-ties and components like LC filters, ferrite cores and jumpers in the power nets.

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Courtyards are intended to keep a safe component clearance when using a pick and place machine.
The net-tie is not a component that must be placed, it is just a copper segment.
Then the courtyard DRC error is only a warning that can be ignored in this specific case.

I don’t think it even makes any sense for the net tie footprints to have a courtyard.

They can be used as locations where the connection can be cut with a knife. It makes sense to have a courtyard to prevent covering it.

Any surface track can be used for that, likewise the normally-closed jumper would be better suited for that

As oppose to a net-tie which is almost exclusively used because different signal names and/or constraints are required at different points on a net that are electrically equivalent. One of the main usage of this is for kelvin connections and thus would appear under a part.

Luckily nothing a custom library entry can’t resolve

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Me either. I also add a fab note “This board has intentional shorts…” but even then it usually still requires email communication to sort out. Recently I had a board vendor send a screenshot of this fab note when asking questions and then also report broken and shorted nets which were the result of not understanding/following this note. Sigh…

Hi all,

some news for anyone using our Smart Test, we are about to add a possibility to document these net ties. They are frequently used and it is often confusing as it is obviously reported as a short.
One good thing about them, you always know that the PCB has been checked properly :wink:


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@aisler do you know if the industry is heading towards any standard way of documenting this, or will it be still a manufacturer-specific convention?

Personally I think we are heading more towards more descriptive formats such as IPC 2581 compared to „single purpose“ formats like IPC 356 A. In IPC 2581 it is rather simple to properly document a net tie.
Same happens with the Gerber file format, while the standard 274 was just aperture definitions and where and how to use them on a canvas, x2 and x3 added way more “meta information” to it. This helps to properly understand the data.

We prefer to use the KiCad files directly as this enables us to extract such information. Regarding net list however we rely on the IPC export and do not add any “extras”.


For info, Gerber X2 format flags copper shapes inside a footprint (that can create and frequently create short circuits, and that can happen in more foorprints than net ties) with the attribute “EtchedComponent” in metadata “TA.AperFunction”.

The aperture used to draw this shape has an associated metadate like:

This is one of advantages of X2 format.