KiCad Version 7.0.6 release build, Windows 10, 64-bit.
Net tie is failing DRC. Two error indicator arrows are shown on the layout but the errors are not itemized in the DRC dialog. Clicking on an indicator shows a message at the bottom of the layout window showing a zone clearance violation.
My research shows this may be a known issue. Is there are workaround other than ignoring the errors?
Is there a setting I’m missing that will allow the errors to be displayed in the DRC dialog window?
If you hit the check box at the bottom of the DRC window next to Errors, does it display anything different? (EDIT: possible that there is an issue with net ties and zones, but I’m guessing the specific DRC errors are being hidden by the checkbox and that will help a lot in diagnosing next steps)
I can exclude the errors for now. I’m still not sure why they are flagged. This was a V6 layout I was making changes to in V7 when this error popped up. These errors were not flagged in V6.
With that context, I agree that this is a variant of the underlying bug in the issue you pointed to. Unfortunately, I wouldn’t hold your breath for a quick resolution (other than excluding those violations from DRC by hand). Looks like a fix for it has been pushed to v8. EDIT: definitely give that issue a “thumbs up” to show that you are affected though!
Since copper graphics still don’t have a real net, they will always cause clearance violations to other things nearby. To demonstrate, I pulled the zones back away from the center of the net-tie and the DRC errors go away.
OT: Are you sure you want to use a net tie, and not use a single net? Net tie can cause more EMC radiations and should be avoided in general.
And if you really want to split GNDs, don’t cross the gap with any track. If you have cross a track, make sure there is no gap underneath and the plane is continues there.
It does appear that the issue is related to the polygon in the net tie. What you’ve demonstrated looks like a good work around, maybe with square pads. Thanks.
I’m rarely sure about anything. This issue cropped up on a purely analog PCB, an audio amplifier. The prevailing wisdom for those guys is to keep the power amplifier output and power returns separate from the signal input returns. Sometimes I use a split plane, other times its careful placement of components and a single plane for such things as low power (<1W) amplifiers.
My understanding is that EMI issues can occur when high speed digital switching circuits are in play. I’m not an electrical engineer, however, so my knowledge is always suspect.
My understanding is that EMI issues can occur when high speed digital switching circuits are in play. I’m not an electrical engineer, however, so my knowledge is always suspect.
Yes, when you define “high speed digital switching circuits” correctly. One thing that can create EMI radiation are the edges, or more precise the dV/dt and dI/dt, i.e. how steep your edges are. It doesn’t matter if a digital IC uses 10 kHz or 100 MHz, the edges can be just as steep with 10 kHz.
But i don’t know much about pure analogue circuits either.
Is that the tab in footprint properties with the pads “1, 2” table? (As opposed to the v6 “net-tie” keyword?) If so, the footprint already is set up for that. The error isn’t the pad to copper polygon overlap, just the external zone to polygon overlap (I got the sense that part wasn’t resolved yet based on the issue).
Following up on this. I believe that I have the net tie footprint properly defined, pads 1,2 are listed as allowed to short different nets.
As scandey observes, it does appear that the F.Cu polygon in the net tie footprint will honor the clearance property of the pour on the PCB, at least in version 7.0.6, which throws the error. The net tie footprint is attached for reference.
