I like to give every net in my schematic a net label such that it is easier during layout to keep track of which nets are around my components, instead of the cryptic defaults. For more complex designs I fear, that I accidentally use two similar names and connect two nets that should NOT be connected. Is there a way to disable this connection feature? Or a tool that shows me all nets that were automatically connected via a net label, such that I can check manually?
I moved from OrCAD and must say, that I’m pretty impressed so far
Keep up this great work
What you ask for is not really possible. The netname is after all what is used to decide the connection.
In general if your schematic is too complex to keep track of the used labels then you have too much in a single unit. I suggest a hierarchical approach where every single design unit is small enough to parse it at a glance.
If you use local or hierarchical nets for this then you do not need to worry about what is used elsewhere in the schematic (it creates knowledge domains).
See Hierarchical or flat schematic design, what is best for me? (How to deal with multi page schematics?)
What could however be a good option would be a better way to get the default net names. One could imagine that the pin name instead of the pin number would help. And some way to prioritize certain symbols for this algorithm.
I will test the approach with hierarchical sheets, this sounds like a nice solution. Thanks!
Changing how the default net names are generated is not possible at the moment isn’t it? This feature would be nice but it has no priority for me. Though should I open a wish list issue on GitLab?
It is not possible at the moment, default net names are driven by component designator and pin number if no other label is present. I suggest opening a feature request, it is probably possible to consider pin name as well.
In KiCad it’s legal to connect diferent labels together with a wire.
Pcbnew then just pics a name, I think in alfabetical order, but I’m not sure.
So these labels get connected without any warning whatsoever:
In my experience, when I do the layout of a board for which I’ve just designed the schematic I tend to spot most accidental errors quite easily.
For example, If I routing to a pin for which I know should be a small net, and suddenly it’s connected to 10 other pins, it rings a bell in my head.
Hierarchical sheets work pretty good, but do take some time to get used to.
Try to start with a simple hierarchical sheet untill you know how it works. In such a simple example open both Eeschema and Pcbnew and regularly update with [F8], so you can immediately see when things get connected and when not.
The highlight net function could help in some way. Second icon on the righthand toolbar.
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