Net connectivity through two heirarchical blocks

I have a main sch sheet, with two heirarchical blocks (HBs).
Each HB has a port with the same name.
Those two ports are connected together.
They don’t go to anything on the main sheet, by the way, maybe that matters.
Inside each HB, that net is connected to something. I’ve triple checked that all the net names are exactly the same - no “O/0” or “I/L” problem. No spaces, no double-underscores.
On the layout, the net names are exactly the same, but they are not connected.
If I try to route them, it doesn’t let me, so it thinks they are not the same net.
Is this a bug?

Check on the PCB-side of things, if you select the net and hit ‘E’. or look in the lower left corner of pcbnew then net will be named “/SheetName/NetName” ?
So the net names are sheet specific and if you want global names use global labels?

My guess: you used local labels instead of global ones. Local nets are prefixed with their hierarchy path. However this full info is not always shown (i think in stable it is only visible if you check the pad properties not in the netname that is rendered on top of the pad)

However my personal view is that hierarchical sheets should only ever use hierarchical pins and have connections made one abstraction layer up (so in the sheet that instantiates the sheet in question).

You might want to read: Hierarchical or flat schematic design, what is best for me? (How to deal with multi page schematics?)

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.