I routed a large portion of a PCB then decided to create a custom net class for the 5V net and change the clearance to 0.4mm. I had thought it was set to 0.2mm, as shown by the “Default” net class, but all net clearance were actually at 0.127mm, which is the Design Rules minimum track clearance setting. Older versions of KiCAD defaulted nets to the Default net class rules, not the Design Rule minimums which is somewhat confusing.
As for the actual problem, when I go to route my 5V net, you can see in the image below that it has the correct clearance when it’s next to other pads, but it allows me to place it as close as the Design Rule minimum of 0.127mm around other nets and I don’t know what’s causing this. I’m running the latest Windows build 8.0.4.
What is that purple shadow around the pads? Does it have something do to with solder mask expansion?
If so, there is always some tolerance for relative position between all layers during fabrication, and it’s likely to expose some of the copper from the A1_5V net.
The thin line around the pad 4 of the +5V net is also a clearance line, and it overlaps with the copper of A1_5V, and this is a DRC violation.
If the mouse / track is in that position, can you fix it’s position with a left click? Then you can use PCB Editor / Inspect / Clearance Resolution to get more info about what KiCad thinks it is.
Are you using any custom rules (In PCB Editor / File / Board Setup / Design Rules / Custom Rules? KiCad has some issues with custom rules (but it’s being worked on).
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Just as you posted that I realized there are a bunch of custom rules set on this project, which I believe are the manufacturing capabilities of JLPCB. The project started in KiCAD 7, and has had a few revisions since then, and I had forgotten these were still in there.
Doing the inspection shows that the custom rules are in fact overriding all others:
Removing the custom rules fixed the issue.
(version 1)
#Kicad 7
# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
(constraint track_width (min 5mil))
(layer outer)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (outer layer)"
(constraint clearance (min 5mil))
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type"))
# 4-layer
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 3.5mil))
(layer inner)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (inner layer)"
(constraint clearance (min 3.5mil))
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type"))
# silkscreen (Kicad 7 only)
(rule "Minimum Text"
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
(layer "?.Silkscreen"))
(rule "Pad to Silkscreen"
(constraint silk_clearance (min 0.15mm))
(layer outer)
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
# edge clearance
(rule "Trace to Outline"
(constraint edge_clearance (min 0.2mm))
(condition "A.Type == 'track'"))
# This would override board outline and milled areas
#(rule "Trace to V-Cut"
# (constraint clearance (min 0.4mm))
# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
# drill/hole size
(rule "drill hole size (mechanical)"
(constraint hole_size (min 0.2mm) (max 6.3mm)))
(rule "Minimum Via Hole Size"
(constraint hole_size (min 0.2mm))
(condition "A.Type == 'via'"))
(rule "Minimum Via Diameter"
(constraint via_diameter (min 0.45mm))
(condition "A.Type == 'via'"))
(rule "PTH Hole Size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated()"))
(rule "Minimum Non-plated Hole Size"
(constraint hole_size (min 0.5mm))
(condition "A.Type == 'pad' && !A.isPlated()"))
(rule "Minimum Castellated Hole Size"
(constraint hole_size (min 0.6mm))
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
# clearance
(rule "hole to hole clearance (different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Net != B.Net"))
(rule "via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'track'"))
(rule "via to via clearance (same nets)"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
(rule "pad to pad clearance (with hole, different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "pad to pad clearance (without hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "NPTH to Track clearance)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
(rule "PTH to Track clearance)"
(constraint hole_clearance (min 0.33mm))
(condition "A.isPlated() && B.Type == 'track'"))
(rule "Pad to Track clearance)"
(constraint clearance (min 0.2mm))
(condition "A.isPlated() && B.Type == 'track'"))
One of the reasons I liked KiCad very much 10 years ago was everything was relatively simple and straight forward. KiCad has made a tremendous amount of progress in the last 10 years, but that part has been slipping through my fingers for a while now. My own KiCad knowledge has been growing with KiCad over the years, but this probably can be a bit problematic when you start with KiCad.
Although, custom rules simply do not exist and do nothing if you do not set them up somehow. Loading such a set of rules without knowing what they do can easily get you into trouble. It looks like these rules are supposed to be reviewed / edited before use. I see references to 2-layer and to 4-layer PCB’s.
I am also just getting started with these custom rules myself. If those rules are manufacturing limits, they should not be in these custom rules but (as much as possible) in PCB Editor / File / Board Setup / Constraints.
Most PCB manufacturers also recommend to use coarser rules then the “absolute minimum” they post on their websites to improve reliability.
